8
Circuit Description
fier Q2020 (2SC3357), driver amplifier Q2014
(RD01MUS1), and then the amplified transmit signal is
applied to the final amplifier Q2008 (RD07MVS1), which
delivers up to 5 watts of output power.
The transmit signal then passes through the antenna switch
D2004 (RLS135) and is low-pass filtered, to suppress har-
monic spurious radiation before delivery to the antenna.
Automatic Transmit Power Control
Current from the final amplifier is sampled by R2015,
R2038 and R2040, and is rectified by Q2003 (IMZ2A).
The resulting DC is fed back through Q2002 (UMX1) to
the drive amplifier Q2014 and final amplifier Q2008, for
control of the power output.
The microprocessor selects “High” or “Low” power levels.
Transmit Inhibit
When the transmit PLL is unlocked, pin 18 of PLL IC
Q2042 (SA7025DK) goes to a logic “Low.” The result-
ing DC unlock control voltage is passed to pin 10 of the
microprocessor Q2047. While the transmit PLL is un-
locked, pin 31 of Q2047 remains high, which then turns
off Q2012 (CPH6102) and the Automatic Power Con-
troller Q2002 (UMX1) to disable the supply voltage to
drive amplifier Q2014/Q2020 and final amplifier Q2008,
thereby disabling the transmitter.
Spurious Suppression
Generation of spurious products by the transmitter is
minimized by the fundamental carrier frequency being
equal to final transmitting frequency, modulated directly
in the transmit VCO. Additional harmonic suppression is
provided by a low-pass filter consisting of coils L2002,
and L2003 plus capacitors C2001, C2002, C2021, C2023,
C2024, C2025, C2026, and C2027, resulting in more than
60 dB of harmonic suppression prior to delivery of the RF
signal to the antenna.
PLL Frequency Synthesizer
The PLL circuitry on the MAIN-2 Unit consists of VCO
Q2030 (2SK210GR), Q2033 (2SC5226), VCO buffer
Q2026 (2SC5005), and PLL subsystem IC Q2042
(SA7025DK), which contains a reference divider, serial-
to-parallel data latch, programmable divider, phase com-
parator and charge pump, and TCXO unit X2002
(TTS05VS) which yields frequency stability of ±2.5ppm
@ –22 °F to +140 °F (–30 °C to +60 °C).
While receiving, VCO Q2030 oscillates between
196.85 and 224.85 MHz according to the transceiver ver-
sion and the programmed receiving frequency. The VCO
output is buffered by Q2026, then applied to the prescaler
section of Q2042. There the VCO signal is divided by 64
or 65, according to a control signal from the data latch
section of Q2042, before being sent to the programmable
divider section of Q2042.
The data latch section of Q2042 also receives serial
dividing data from the microprocessor Q2047, which
causes the pre-divided VCO signal to be further divided
in the programmable divider section, depending upon the
desired receive frequency, so as to produce a 5.0 kHz or
6.25 kHz derivative of the current VCO frequency.
Meanwhile, the reference divider section of Q2042 di-
vides the 16.80 MHz crystal reference from the reference
oscillator Q2051, by 3360 (or 2688) to produce the 5.0
kHz (or 6.25 kHz) loop references (respectively).
The 5.0 kHz (or 6.25 kHz) signal from the program-
mable divider (derived from the VCO) and that derived
from the reference oscillator are applied to the phase de-
tector section of Q2042, which produces a pulsed output
with pulse duration depending on the phase difference be-
tween the input signals.
This pulse train is filtered to DC and returned to
varactors D2021, D2022, D2023, and D2024 (all
HVD372B). Changes in the level of the DC voltage are
applied to the varactors, affecting the reference in the tank
circuit of the VCO according to the phase difference be-
tween the signals derived from the VCO and the crystal
reference oscillator.
The VCO is thus phase-locked to the crystal reference
oscillator. The output of the VCO Q2030 (2SK210GR),
after buffering by Q2026, is applied to the first mixer as
described previously.
For transmission, the VCO Q2033 (2SK210GR) os-
cillates between 146.00 and 174.00 MHz according to the
model version and programmed transmit frequency. The
remainder of the PLL circuitry is shared with the receiver.
However, the dividing data from the microprocessor is such
that the VCO frequency is at the actual transmit frequency
(rather than offset for IFs, as in the receiving case). Also,
the VCO is modulated by the speech audio applied to
D2017 (HVC350B), as described previously.
Receive and transmit buses select which VCO is made
active, using Q2028 (DTC144EE), Q2031 (DTC124TE),
Q2032 (DTC144EE).
Miscellaneous Circuits
Push-To-Talk Transmit Activation
The PTT switch on the microphone is connected to pin
22 of microprocessor Q2047, so that when the PTT switch
is closed, pin 27 of Q2047 goes high. This signal disables
the receiver by disabling the 5V supply bus at Q2022
(DTB123EK) to the front-end, FM IF subsystem IC
Q2048 and the receiver VCO circuitry.
At the same time, Q2013 (UMX1N) and Q2012
(CPH6102) activate the transmit 5V supply line to en-
able the transmitter.
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