VIPA CPU 312SC - Page 41

Order no. 312-5BE13
Maximum nesting depth per priority class 8
Maximum nesting depth additional within an
error OB
4
Time
Real-time clock buffered
ü
Clock buffered period (min.) 6 w
Accuracy (max. deviation per day) 10 s
Number of operating hours counter 8
Clock synchronization
ü
Synchronization via MPI Master/Slave
Synchronization via Ethernet (NTP) no
Address areas (I/O)
Input I/O address area 1024 Byte
Output I/O address area 1024 Byte
Input process image maximal 128 Byte
Output process image maximal 128 Byte
Digital inputs 272
Digital outputs 264
Digital inputs central 272
Digital outputs central 264
Integrated digital inputs 16
Integrated digital outputs 8
Analog inputs 64
Analog outputs 64
Analog inputs, central 64
Analog outputs, central 64
Integrated analog inputs 0
Integrated analog outputs 0
Communication functions
PG/OP channel
ü
Global data communication
ü
Number of GD circuits, max. 4
Size of GD packets, max. 22 Byte
S7 basic communication
ü
S7 basic communication, user data per job 76 Byte
S7 communication
ü
VIPA System 300S Hardware description
Technical data
HB140 | CPU-SC | 312-5BE13 | GB | 15-50 41