Xilinx KC705 User Manual

KC705 Evaluation Board 105
UG810 (v1.8) March 20, 2018 www.xilinx.com
Appendix C: Master Constraints File Listing
set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_SPDIF]
set_property PACKAGE_PIN H20 [get_ports HDMI_R_VSYNC]
set_property IOSTANDARD LVCMOS25 [get_ports HDMI_R_VSYNC]
set_property PACKAGE_PIN G20 [get_ports HDMI_SPDIF_OUT_LS]
set_property IOSTANDARD LVCMOS25 [get_ports HDMI_SPDIF_OUT_LS]
#IIC
set_property PACKAGE_PIN P23 [get_ports IIC_MUX_RESET_B]
set_property IOSTANDARD LVCMOS25 [get_ports IIC_MUX_RESET_B]
set_property PACKAGE_PIN K21 [get_ports IIC_SCL_MAIN]
set_property IOSTANDARD LVCMOS25 [get_ports IIC_SCL_MAIN]
set_property PACKAGE_PIN L21 [get_ports IIC_SDA_MAIN]
set_property IOSTANDARD LVCMOS25 [get_ports IIC_SDA_MAIN]
#PCIE
set_property PACKAGE_PIN M5 [get_ports PCIE_RX0_N]
set_property PACKAGE_PIN M6 [get_ports PCIE_RX0_P]
set_property PACKAGE_PIN P5 [get_ports PCIE_RX1_N]
set_property PACKAGE_PIN P6 [get_ports PCIE_RX1_P]
set_property PACKAGE_PIN R3 [get_ports PCIE_RX2_N]
set_property PACKAGE_PIN R4 [get_ports PCIE_RX2_P]
set_property PACKAGE_PIN T5 [get_ports PCIE_RX3_N]
set_property PACKAGE_PIN T6 [get_ports PCIE_RX3_P]
set_property PACKAGE_PIN V5 [get_ports PCIE_RX4_N]
set_property PACKAGE_PIN V6 [get_ports PCIE_RX4_P]
set_property PACKAGE_PIN W3 [get_ports PCIE_RX5_N]
set_property PACKAGE_PIN W4 [get_ports PCIE_RX5_P]
set_property PACKAGE_PIN Y5 [get_ports PCIE_RX6_N]
set_property PACKAGE_PIN Y6 [get_ports PCIE_RX6_P]
set_property PACKAGE_PIN AA3 [get_ports PCIE_RX7_N]
set_property PACKAGE_PIN AA4 [get_ports PCIE_RX7_P]
set_property PACKAGE_PIN L3 [get_ports PCIE_TX0_N]
set_property PACKAGE_PIN L4 [get_ports PCIE_TX0_P]
set_property PACKAGE_PIN M1 [get_ports PCIE_TX1_N]
set_property PACKAGE_PIN M2 [get_ports PCIE_TX1_P]
set_property PACKAGE_PIN N3 [get_ports PCIE_TX2_N]
set_property PACKAGE_PIN N4 [get_ports PCIE_TX2_P]
set_property PACKAGE_PIN P1 [get_ports PCIE_TX3_N]
set_property PACKAGE_PIN P2 [get_ports PCIE_TX3_P]
set_property PACKAGE_PIN T1 [get_ports PCIE_TX4_N]
set_property PACKAGE_PIN T2 [get_ports PCIE_TX4_P]
set_property PACKAGE_PIN U3 [get_ports PCIE_TX5_N]
set_property PACKAGE_PIN U4 [get_ports PCIE_TX5_P]
set_property PACKAGE_PIN V1 [get_ports PCIE_TX6_N]
set_property PACKAGE_PIN V2 [get_ports PCIE_TX6_P]
set_property PACKAGE_PIN Y1 [get_ports PCIE_TX7_N]
set_property PACKAGE_PIN Y2 [get_ports PCIE_TX7_P]
set_property PACKAGE_PIN U7 [get_ports PCIE_CLK_QO_N]
set_property PACKAGE_PIN U8 [get_ports PCIE_CLK_QO_P]
set_property PACKAGE_PIN G25 [get_ports PCIE_PERST_LS]
set_property IOSTANDARD LVCMOS25 [get_ports PCIE_PERST_LS]
set_property PACKAGE_PIN F23 [get_ports PCIE_WAKE_B_LS]
set_property IOSTANDARD LVCMOS25 [get_ports PCIE_WAKE_B_LS]
#ETHERNET
set_property PACKAGE_PIN U27 [get_ports PHY_RXCLK]
set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXCLK]
set_property PACKAGE_PIN U30 [get_ports PHY_RXD0]
set_property IOSTANDARD LVCMOS25 [get_ports PHY_RXD0]
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Xilinx KC705 Specifications

General

Brand	Xilinx
Model	KC705
Category	Motherboard
Language	English