Xilinx KC705 User Manual

KC705 Evaluation Board 15
UG810 (v1.8) March 20, 2018 www.xilinx.com
Chapter 1: KC705 Evaluation Board Features
Table 1-4: DDR3 Memory Connections to the FPGA
U1 FPGA
Pin
Net Name I/O Standard
J1 DDR3 Memory
Pin
Number
Pin Name
AH12 DDR3_A0 SSTL15 98 A0
AG13 DDR3_A1 SSTL15 97 A1
AG12 DDR3_A2 SSTL15 96 A2
AF12 DDR3_A3 SSTL15 95 A3
AJ12 DDR3_A4 SSTL15 92 A4
AJ13 DDR3_A5 SSTL15 91 A5
AJ14 DDR3_A6 SSTL15 90 A6
AH14 DDR3_A7 SSTL15 86 A7
AK13 DDR3_A8 SSTL15 89 A8
AK14 DDR3_A9 SSTL15 85 A9
AF13 DDR3_A10 SSTL15 107 A10/AP
AE13 DDR3_A11 SSTL15 84 A11
AJ11 DDR3_A12 SSTL15 83 A12_BC_N
AH11 DDR3_A13 SSTL15 119 A13
AK10 DDR3_A14 SSTL15 80 A14
AK11 DDR3_A15 SSTL15 78 A15
AH9 DDR3_BA0 SSTL15 109 BA0
AG9 DDR3_BA1 SSTL15 108 BA1
AK9 DDR3_BA2 SSTL15 79 BA2
AA15 DDR3_D0 SSTL15 5 DQ0
AA16 DDR3_D1 SSTL15 7 DQ1
AC14 DDR3_D2 SSTL15 15 DQ2
AD14 DDR3_D3 SSTL15 17 DQ3
AA17 DDR3_D4 SSTL15 4 DQ4
AB15 DDR3_D5 SSTL15 6 DQ5
AE15 DDR3_D6 SSTL15 16 DQ6
Y15 DDR3_D7 SSTL15 18 DQ7
AB19 DDR3_D8 SSTL15 21 DQ8
AD16 DDR3_D9 SSTL15 23 DQ9
AC19 DDR3_D10 SSTL15 33 DQ10
AD17 DDR3_D11 SSTL15 35 DQ11
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Xilinx KC705 Specifications

General

Brand	Xilinx
Model	KC705
Category	Motherboard
Language	English