Xilinx KC705 User Manual

KC705 Evaluation Board 16
UG810 (v1.8) March 20, 2018 www.xilinx.com
Chapter 1: KC705 Evaluation Board Features
AA18 DDR3_D12 SSTL15 22 DQ12
AB18 DDR3_D13 SSTL15 24 DQ13
AE18 DDR3_D14 SSTL15 34 DQ14
AD18 DDR3_D15 SSTL15 36 DQ15
AG19 DDR3_D16 SSTL15 39 DQ16
AK19 DDR3_D17 SSTL15 41 DQ17
AG18 DDR3_D18 SSTL15 51 DQ18
AF18 DDR3_D19 SSTL15 53 DQ19
AH19 DDR3_D20 SSTL15 40 DQ20
AJ19 DDR3_D21 SSTL15 42 DQ21
AE19 DDR3_D22 SSTL15 50 DQ22
AD19 DDR3_D23 SSTL15 52 DQ23
AK16 DDR3_D24 SSTL15 57 DQ24
AJ17 DDR3_D25 SSTL15 59 DQ25
AG15 DDR3_D26 SSTL15 67 DQ26
AF15 DDR3_D27 SSTL15 69 DQ27
AH17 DDR3_D28 SSTL15 56 DQ28
AG14 DDR3_D29 SSTL15 58 DQ29
AH15 DDR3_D30 SSTL15 68 DQ30
AK15 DDR3_D31 SSTL15 70 DQ31
AK8 DDR3_D32 SSTL15 129 DQ32
AK6 DDR3_D33 SSTL15 131 DQ33
AG7 DDR3_D34 SSTL15 141 DQ34
AF7 DDR3_D35 SSTL15 143 DQ35
AF8 DDR3_D36 SSTL15 130 DQ36
AK4 DDR3_D37 SSTL15 132 DQ37
AJ8 DDR3_D38 SSTL15 140 DQ38
AJ6 DDR3_D39 SSTL15 142 DQ39
AH5 DDR3_D40 SSTL15 147 DQ40
AH6 DDR3_D41 SSTL15 149 DQ41
AJ2 DDR3_D42 SSTL15 157 DQ42
Table 1-4: DDR3 Memory Connections to the FPGA (Cont’d)
U1 FPGA
Pin
Net Name I/O Standard
J1 DDR3 Memory
Pin
Number
Pin Name
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Xilinx KC705 Specifications

General

Brand	Xilinx
Model	KC705
Category	Motherboard
Language	English