Xilinx KC705 User Manual

KC705 Evaluation Board 44
UG810 (v1.8) March 20, 2018 www.xilinx.com
Chapter 1: KC705 Evaluation Board Features
SGMII GTX Transceiver Clock Generator
[Figure 1-2, callout 16]
An Integrated Circuit Systems ICS844021I chip (U2) generates a high-quality, low-jitter,
125 MHz LVDS clock from a 25 MHz crystal (X3). This clock is sent to FPGA U1, bank 117 GTX
transceiver (clock pins G8 (P) and G7 (N)) driving the SGMII interface. Series AC coupling
capacitors are present to allow the clock input of the FPGA to set the common mode
voltage. Figure 1-18 shows the Ethernet SGMII clock source.
Table 1-18 shows the connections and pin numbers for the M88E1111 PHY.
X-Ref Target - Fig ure 1-18
Figure 1-18: Ethernet 125 MHz SGMII GTX Clock
UG810_c1_18_031214
GND_SGMIICLK
VDD_SGMIICLK
ICS844021I-01
Clock Generator
VDDA
GND_SGMIICLK
XTAL_IN
XTAL_OUT
VDD
1
2
3
5
7
6
U2
R134
1.0MΩ 5%
Q0
4
8
NQ0
VDDA_SGMIICLK
C93
18pF 50V
NPO
C94
18pF 50V
NPO
C14
0.1μF 25V
X5R
C15
0.1μF 25V
X5R
SGMIICLK_XTAL_OUT
GND2
GND2
X2
X1
X3
25.00 MHz
SGMIICLK_Q0_P
SGMIICLK_Q0_N
SGMIICLK_Q0_C_P
SGMIICLK_Q0_C_NSGMIICLK_XTAL_IN
GND_SGMIICLK
GND
OE
2
1
3
4
Table 1-18: Ethernet PHY Connections
U1 FPGA Pin Schematic Net Name I/O Standard
M88E1111 (U37)
Pin Number Pin Name
J21 PHY_MDIO LVCMOS25 M1 MDIO
R23 PHY_MDC LVCMOS25 L3 MDC
N30 PHY_INT LVCMOS25 L1 INT_B
L20 PHY_RESET LVCMOS25 K3 RESET_B
R30 PHY_CRS LVCMOS25 B5 CRS
W19 PHY_COL LVCMOS25 B6 COL
U27 PHY_RXCLK LVCMOS25 C1 RXCLK
V26 PHY_RXER LVCMOS25 D2 RXER
R28 PHY_REXCTL_RXDV LVCMOS25 B1 RXDV
U30 PHY_RXD0 LVCMOS25 B2 RXD0
U25 PHY_RXD1 LVCMOS25 D3 RXD1
T25 PHY_RXD2 LVCMOS25 C3 RXD2
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Xilinx KC705 Specifications

General

Brand	Xilinx
Model	KC705
Category	Motherboard
Language	English