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Xilinx KC705 User Manual
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K
C705 E
valua
tion Board
82
UG810 (v1.8) Mar
ch 20, 2018
www
.xilinx.com
Chapter 1:
K
C705 E
valuation Board F
eature
s
X-Ref Target - Fig
ure 1-40
Figure 1-40:
KC705 Board Configur
ation Circuit
UG810_c1_40_070114
RST_B
CLK
WE_B
OE_B
ADV_B
D[15:00]
A[27:01]
U58
P30 1Gb
Flash Memory
D
Q
HOLD_B
W_B
C
S-B
U7
N25Q128A13BSF-40F
QUAD SPI
TCK
TMS
TDI
TDO
Bank 0
CCLK
INIT_B
VCCBATT
M[2:0]
DONE
PROG_B
U1
FPGA
SW14
Bank 15
Bank 14
FWE_B
FOE_B
ADV_B
RS1
RS0
A[26:25]
A[24:16]
A[15:00]
D[15:00]
FCS_B
EMCCLK
CSO_B
PUDC_B
GND
VCCA
UXIO (2.0V)
4.7 k
Ω
GND
27.4
Ω
GND
R405
1 k
Ω
300
Ω
D11
BAS40-04
B1
DS20
GREEN
GND
ETHERNET MDC
U64
Oscillator
66 MHz
SW13
Mode
Switch
CE_B
NC
M0
0
1
P
ar
t of
SW13
GND
U63
Boot Select
Demultiplexer
2.5 V
A[26:00]
A26
A25
S
e
n
d
F
e
e
d
b
a
c
k
81
83
Table of Contents
Default Chapter
2
Revision History
2
Table of Contents
4
Chapter 1: KC705 Evaluation Board Features
6
Overview
6
Feature Descriptions
9
KC705 Board Block Diagram
9
KC705 Board Component Descriptions
10
KC705 Board Components
10
FPGA Configuration
12
Kintex-7 FPGA
12
SW13 Default Settings
12
Encryption Key Backup Circuit
13
I/O Voltage Rails
13
KC705 Board FPGA Configuration Modes
13
DDR3 Memory Module
14
DDR3 Memory Connections to the FPGA
15
BPI Flash Memory Connections to the FPGA
19
Linear BPI Flash Memory
19
MB Linear Flash Memory (U58)
22
Quad SPI Flash Memory
23
Quad SPI Flash Memory Connections to the FPGA
23
Mb Quad SPI Flash Memory
24
SD Card Interface
24
SDIO Connections to the FPGA
25
JTAG Chain Block Diagram
26
USB JTAG Module
26
JTAG Circuit
27
Clock Generation
28
Clock Source to FPGA U1 Connections
28
KC705 Board Clock Sources
28
Programmable User Clock Source
29
System Clock Source
29
User Clock Source
30
User SMA Clock Input
30
GTX SMA Clock Input
31
GTX SMA Clock Source
31
User SMA Clock Source
31
Jitter Attenuated Clock
32
GTX Transceivers
33
GTX Interface Connections for FPGA U1
34
PCI Express Edge Connector
35
PCI Express Clock
36
PCI Express Lane Size Select Jumper J32
36
Pcie Edge Connector Connections
36
GTX Quad 115 Pcie Edge Connector Connections
38
GTX Quad 116 to Pcie Edge Connector Connections
39
SFP+ Module Connector
41
SFP/SFP+ Connector
41
FPGA U1 to SFP+ Module Connections
42
SFP+ Module Control and Status
42
10/100/1000 Tri-Speed Ethernet PHY
43
Board Connections for PHY Configuration Pins
43
PHY Default Interface Mode
43
Ethernet 125 Mhz SGMII GTX Clock
44
Ethernet PHY Connections
44
SGMII GTX Transceiver Clock Generator
44
USB-To-UART Bridge
45
FPGA to UART Connections
46
USB J6 Mini-B Receptacle Pin Assignments and Signal Definitions
46
HDMI Video Output
47
HDMI Codec Circuit
48
FPGA to HDMI Codec Connections (ADV7511)
49
ADV7511 to HDMI Connector Connections
50
LCD Character Display
50
LCD Display
50
LCD Header Details
51
LCD Interface Circuit
51
FPGA to LCD Header Connections
52
I2C Bus Switch
52
I2C Bus Topology
52
I2C Devices
53
Status Leds
53
Ethernet PHY Status Leds
54
User I/O
54
User Leds
55
User Pushbuttons
56
CPU Reset Pushbutton
57
GPIO DIP Switch
57
Rotary Switch
58
Rotary Switch SW8
58
GPIO Connections to FPGA U1
59
GPIO SMA Connectors
59
GPIO Smas J13 and J14
59
Power On/Off Slide Switch SW15
60
Switches
60
ATX Power Supply Adapter Cable
61
FPGA_PROG_B Pushbutton SW14 (Active-Low)
61
Power On/Off Switch SW15
61
Configuration Mode and Upper Linear Flash Address Switch
62
Configuration Mode and Upper Linear Flash Address Switch (SW13)
62
FPGA_PROG_B Pushbutton SW14
62
FPGA Mezzanine Card Interface
63
HPC Connector J22
63
Signaling Speed Ratings
63
HPC Connections, J22 to FPGA U1
64
LPC Connector J2
68
LPC Connections, J2 to FPGA U1
69
Power Management
71
KC705 Board Onboard Power Regulators
72
Auxiliary Voltage Controller and Regulators
73
Core Voltage Controller and Regulators
73
Linear Regulators
73
Onboard Power System Devices
73
Cooling Fan Control
74
FMC_VADJ Voltage Control
74
FPGA Cooling Fan Circuit
75
Monitoring Voltage and Current
75
Power Rail Specifications for UCD9248 Pmbus Controller at Address 52
76
Power Rail Specifications for UCD9248 Pmbus Controller at Address 53
76
Power Rail Specifications for UCD9248 Pmbus Controller at Address 54
77
Header XADC_VREF Voltage Source Options
78
XADC Header
78
XADC Header (J46)
79
XADC Header J46 Pinout
79
Configuration Options
80
Mode Switch SW13 Settings
80
Mode Switch
81
KC705 Board Configuration Circuit
82
A-1: SW11 Default Switch Settings
83
Appendix A: Default Switch and Jumper Settings
83
DIP Switch SW13 Mode and Flash Memory Address Settings
84
Default Jumper Settings
84
KC705 Default Jumper Settings
84
A-3: KC705 Jumper Locations
85
DIP Switch SW11 User GPIO
83
Appendix B: VITA 57.1 FMC Connector Pinouts
86
FMC LPC Connector Pinout
87
KC705 Board XDC Listing
88
Appendix C: Master Constraints File Listing
88
Installing KC705 Board in a PC Chassis
109
To Install the KC705 Board in a PC Chassis
109
Appendix D: Board Setup
109
Dimensions
111
Environmental
111
Operating Voltage
111
Appendix E: Board Specifications
111
Appendix F: Regulatory Compliance and Information
112
Declaration of Conformity
112
Directives
112
Standards
112
Safety
113
Markings
113
Xilinx Resources
114
Solution Centers
114
Documentation Navigator and Design Hubs
114
Appendix G: Additional Resources and Legal Notices
114
References
115
Training Resources
116
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Xilinx KC705 Specifications
General
Brand
Xilinx
Model
KC705
Category
Motherboard
Language
English
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