Xilinx KC705 User Manual

KC705 Evaluation Board 17
UG810 (v1.8) March 20, 2018 www.xilinx.com
Chapter 1: KC705 Evaluation Board Features
AH2 DDR3_D43 SSTL15 159 DQ43
AH4 DDR3_D44 SSTL15 146 DQ44
AJ4 DDR3_D45 SSTL15 148 DQ45
AK1 DDR3_D46 SSTL15 158 DQ46
AJ1 DDR3_D47 SSTL15 160 DQ47
AF1 DDR3_D48 SSTL15 163 DQ48
AF2 DDR3_D49 SSTL15 165 DQ49
AE4 DDR3_D50 SSTL15 175 DQ50
AE3 DDR3_D51 SSTL15 177 DQ51
AF3 DDR3_D52 SSTL15 164 DQ52
AF5 DDR3_D53 SSTL15 166 DQ53
AE1 DDR3_D54 SSTL15 174 DQ54
AE5 DDR3_D55 SSTL15 176 DQ55
AC1 DDR3_D56 SSTL15 181 DQ56
AD3 DDR3_D57 SSTL15 183 DQ57
AC4 DDR3_D58 SSTL15 191 DQ58
AC5 DDR3_D59 SSTL15 193 DQ59
AE6 DDR3_D60 SSTL15 180 DQ60
AD6 DDR3_D61 SSTL15 182 DQ61
AC2 DDR3_D62 SSTL15 192 DQ62
AD4 DDR3_D63 SSTL15 194 DQ63
Y16 DDR3_DM0 SSTL15 11 DM0
AB17 DDR3_DM1 SSTL15 28 DM1
AF17 DDR3_DM2 SSTL15 46 DM2
AE16 DDR3_DM3 SSTL15 63 DM3
AK5 DDR3_DM4 SSTL15 136 DM4
AJ3 DDR3_DM5 SSTL15 153 DM5
AF6 DDR3_DM6 SSTL15 170 DM6
AC7 DDR3_DM7 SSTL15 187 DM7
AC15 DDR3_DQS0_N DIFF_SSTL15 10 DQS0_N
AC16 DDR3_DQS0_P DIFF_SSTL15 12 DQS0_P
Table 1-4: DDR3 Memory Connections to the FPGA (Cont’d)
U1 FPGA
Pin
Net Name I/O Standard
J1 DDR3 Memory
Pin
Number
Pin Name
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Xilinx KC705 Specifications

General

Brand	Xilinx
Model	KC705
Category	Motherboard
Language	English