Xilinx KC705

KC705 Evaluation Board 18
UG810 (v1.8) March 20, 2018 www.xilinx.com
Chapter 1: KC705 Evaluation Board Features
The KC705 DDR3 SODIMM interface adheres to the constraints guidelines documented in
the DDR3 Design Guidelines section of 7 Series FPGAs Memory Interface Solutions
Y18 DDR3_DQS1_N DIFF_SSTL15 27 DQS1_N
Y19 DDR3_DQS1_P DIFF_SSTL15 29 DQS1_P
AK18 DDR3_DQS2_N DIFF_SSTL15 45 DQS2_N
AJ18 DDR3_DQS2_P DIFF_SSTL15 47 DQS2_P
AJ16 DDR3_DQS3_N DIFF_SSTL15 62 DQS3_N
AH16 DDR3_DQS3_P DIFF_SSTL15 64 DQS3_P
AJ7 DDR3_DQS4_N DIFF_SSTL15 135 DQS4_N
AH7 DDR3_DQS4_P DIFF_SSTL15 137 DQS4_P
AH1 DDR3_DQS5_N DIFF_SSTL15 152 DQS5_N
AG2 DDR3_DQS5_P DIFF_SSTL15 154 DQS5_P
AG3 DDR3_DQS6_N DIFF_SSTL15 169 DQS6_N
AG4 DDR3_DQS6_P DIFF_SSTL15 171 DQS6_P
AD1 DDR3_DQS7_N DIFF_SSTL15 186 DQS7_N
AD2 DDR3_DQS7_P DIFF_SSTL15 188 DQS7_P
AD8 DDR3_ODT0 SSTL15 116 ODT0
AC10 DDR3_ODT1 SSTL15 120 ODT1
AK3 DDR3_RESET_B LVCMOS15 30 RESET_B
AC12 DDR3_S0_B SSTL15 114 S0_B
AE8 DDR3_S1_B SSTL15 121 S1_B
AJ9 DDR3_TEMP_EVENT SSTL15 198 EVENT_B
AE9 DDR3_WE_B SSTL15 113 WE_B
AC11 DDR3_CAS_B SSTL15 115 CAS_B
AD9 DDR3_RAS_B SSTL15 110 RAS_B
AF10 DDR3_CKE0 SSTL15 73 CKE0
AE10 DDR3_CKE1 SSTL15 74 CKE1
AH10 DDR3_CLK0_N DIFF_SSTL15 103 CK0_N
AG10 DDR3_CLK0_P DIFF_SSTL15 101 CK0_P
AF11 DDR3_CLK1_N DIFF_SSTL15 104 CK1_N
AE11 DDR3_CLK1_P DIFF_SSTL15 102 CK1_P
Table 1-4: DDR3 Memory Connections to the FPGA (Cont’d)
U1 FPGA
Pin
Net Name I/O Standard
J1 DDR3 Memory
Pin
Number
Pin Name
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