Xilinx KC705 User Manual

KC705 Evaluation Board 107
UG810 (v1.8) March 20, 2018 www.xilinx.com
Appendix C: Master Constraints File Listing
set_property PACKAGE_PIN G8 [get_ports SGMIICLK_Q0_P]
#PMBUS
set_property PACKAGE_PIN AB14 [get_ports PMBUS_ALERT_LS]
set_property IOSTANDARD LVCMOS15 [get_ports PMBUS_ALERT_LS]
set_property PACKAGE_PIN AG17 [get_ports PMBUS_CLK_LS]
set_property IOSTANDARD LVCMOS15 [get_ports PMBUS_CLK_LS]
set_property PACKAGE_PIN Y14 [get_ports PMBUS_DATA_LS]
set_property IOSTANDARD LVCMOS15 [get_ports PMBUS_DATA_LS]
#SDIO
set_property PACKAGE_PIN AC20 [get_ports SDIO_DAT0_LS]
set_property IOSTANDARD LVCMOS25 [get_ports SDIO_DAT0_LS]
set_property PACKAGE_PIN AA23 [get_ports SDIO_DAT1_LS]
set_property IOSTANDARD LVCMOS25 [get_ports SDIO_DAT1_LS]
set_property PACKAGE_PIN AA22 [get_ports SDIO_DAT2_LS]
set_property IOSTANDARD LVCMOS25 [get_ports SDIO_DAT2_LS]
set_property PACKAGE_PIN AC21 [get_ports SDIO_CD_DAT3_LS]
set_property IOSTANDARD LVCMOS25 [get_ports SDIO_CD_DAT3_LS]
set_property PACKAGE_PIN AB23 [get_ports SDIO_CLK_LS]
set_property IOSTANDARD LVCMOS25 [get_ports SDIO_CLK_LS]
set_property PACKAGE_PIN AB22 [get_ports SDIO_CMD_LS]
set_property IOSTANDARD LVCMOS25 [get_ports SDIO_CMD_LS]
set_property PACKAGE_PIN AA21 [get_ports SDIO_SDDET]
set_property IOSTANDARD LVCMOS25 [get_ports SDIO_SDDET]
set_property PACKAGE_PIN Y21 [get_ports SDIO_SDWP]
set_property IOSTANDARD LVCMOS25 [get_ports SDIO_SDWP]
#SFP
set_property PACKAGE_PIN G4 [get_ports SFP_RX_N]
set_property PACKAGE_PIN G3 [get_ports SFP_RX_P]
set_property PACKAGE_PIN H1 [get_ports SFP_TX_N]
set_property PACKAGE_PIN H2 [get_ports SFP_TX_P]
set_property PACKAGE_PIN P19 [get_ports SFP_LOS_LS]
set_property IOSTANDARD LVCMOS25 [get_ports SFP_LOS_LS]
set_property PACKAGE_PIN Y20 [get_ports SFP_TX_DISABLE]
set_property IOSTANDARD LVCMOS25 [get_ports SFP_TX_DISABLE]
#FAN
set_property PACKAGE_PIN L26 [get_ports SM_FAN_PWM]
set_property IOSTANDARD LVCMOS25 [get_ports SM_FAN_PWM]
set_property PACKAGE_PIN U22 [get_ports SM_FAN_TACH]
set_property IOSTANDARD LVCMOS25 [get_ports SM_FAN_TACH]
#USB UART
set_property PACKAGE_PIN L27 [get_ports USB_CTS]
set_property IOSTANDARD LVCMOS25 [get_ports USB_CTS]
set_property PACKAGE_PIN K23 [get_ports USB_RTS]
set_property IOSTANDARD LVCMOS25 [get_ports USB_RTS]
set_property PACKAGE_PIN K24 [get_ports USB_RX]
set_property IOSTANDARD LVCMOS25 [get_ports USB_RX]
set_property PACKAGE_PIN M19 [get_ports USB_TX]
set_property IOSTANDARD LVCMOS25 [get_ports USB_TX]
Note: Regarding USB UART—The XDC constraints for pins K24 and M19 do not match those in the
Vivado part0_pins.xml file. See Kintex-7 KC705 FGPA Evaluation Kit Master Answer Record (AR
45934) for more information.
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Xilinx KC705 Specifications

General

Brand	Xilinx
Model	KC705
Category	Motherboard
Language	English