KC705 Evaluation Board 21
UG810 (v1.8) March 20, 2018 www.xilinx.com
Chapter 1: KC705 Evaluation Board Features
Additional FPGA bitstreams can be stored and used for configuration by setting the Warm
Boot Start Address (WBSTAR) register contained in 7 series FPGAs. More information is
available in the reconfiguration and multiboot section in 7 Series FPGAs Configuration
User Guide (UG470) [Ref 2]. The configuration section in this document provides details on
the Master BPI configuration mode.
P28 FLASH_D12 LVCMOS25 F5 DQ12
T30 FLASH_D13 LVCMOS25 H5 DQ13
P26 FLASH_D14 LVCMOS25 G7 DQ14
R26 FLASH_D15 LVCMOS25 E7 DQ15
U29 FLASH_WAIT LVCMOS25 F7 WAIT
M25 FPGA_FWE_B LVCMOS25 G8 WE_B
M24 FLASH_OE_B LVCMOS25 F8 OE_B
B10 FPGA_CCLK LVCMOS25 E6 CLK
U63.6 FLASH_CE_B LVCMOS25 B4 CE_B
M30 FLASH_ADV_B LVCMOS25 F6 ADV_B
A10 FPGA_INIT_B LVCMOS25 D4 RST_B
Table 1-5: BPI Flash Memory Connections to the FPGA (Cont’d)
U1 FPGA Pin Net Name I/O Standard
U58 BPI Flash Memory
Pin Number Pin Name
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