Xilinx KC705 User Manual

KC705 Evaluation Board 37
UG810 (v1.8) March 20, 2018 www.xilinx.com
Chapter 1: KC705 Evaluation Board Features
PCIE_RX3_N T5 B28 PETn3 Integrated Endpoint block
receive pair
GTXE2_CHANNEL_X0Y4
PCIE_RX4_P V6 B33 PETp4 Integrated Endpoint block
receive pair
GTXE2_CHANNEL_X0Y3
PCIE_RX4_N V5 B34 PETn4 Integrated Endpoint block
receive pair
GTXE2_CHANNEL_X0Y3
PCIE_RX5_P W4 B37 PETp5 Integrated Endpoint block
receive pair
GTXE2_CHANNEL_X0Y2
PCIE_RX5_N W3 B38 PETn5 Integrated Endpoint block
receive pair
GTXE2_CHANNEL_X0Y2
PCIE_RX6_P Y6 B41 PETp6 Integrated Endpoint block
receive pair
GTXE2_CHANNEL_X0Y1
PCIE_RX6_N Y5 B42 PETn6 Integrated Endpoint block
receive pair
GTXE2_CHANNEL_X0Y1
PCIE_RX7_P AA4 B45 PETp7 Integrated Endpoint block
receive pair
GTXE2_CHANNEL_X0Y0
PCIE_RX7_N AA3 B46 PETn7 Integrated Endpoint block
receive pair
GTXE2_CHANNEL_X0Y0
PCIE_TX0_P L4 A16 PERp0 Integrated Endpoint block
transmit pair
GTXE2_CHANNEL_X0Y7
PCIE_TX0_N L3 A17 PERn0 Integrated Endpoint block
transmit pair
GTXE2_CHANNEL_X0Y7
PCIE_TX1_P M2 A21 PERp1 Integrated Endpoint block
transmit pair
GTXE2_CHANNEL_X0Y6
PCIE_TX1_N M1 A22 PERn1 Integrated Endpoint block
transmit pair
GTXE2_CHANNEL_X0Y6
PCIE_TX2_P N4 A25 PERp2 Integrated Endpoint block
transmit pair
GTXE2_CHANNEL_X0Y5
PCIE_TX2_N N3 A26 PERn2 Integrated Endpoint block
transmit pair
GTXE2_CHANNEL_X0Y5
PCIE_TX3_P P2 A29 PERp3 Integrated Endpoint block
transmit pair
GTXE2_CHANNEL_X0Y4
PCIE_TX3_N P1 A30 PERn3 Integrated Endpoint block
transmit pair
GTXE2_CHANNEL_X0Y4
PCIE_TX4_P T2 A35 PERp4 Integrated Endpoint block
transmit pair
GTXE2_CHANNEL_X0Y3
PCIE_TX4_N T1 A36 PERn4 Integrated Endpoint block
transmit pair
GTXE2_CHANNEL_X0Y3
Table 1-11: PCIe Edge Connector Connections (Cont’d)
Schematic Net
Name
FPGA Pin
(U1)
PCIe Edge
Connector
Pin
PCIe Edge
Pin Name
Function FFG900 Placement
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Xilinx KC705 Specifications

General

Brand	Xilinx
Model	KC705
Category	Motherboard
Language	English