Xilinx KC705 User Manual

KC705 Evaluation Board 93
UG810 (v1.8) March 20, 2018 www.xilinx.com
Appendix C: Master Constraints File Listing
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM5]
set_property PACKAGE_PIN AF6 [get_ports DDR3_DM6]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM6]
set_property PACKAGE_PIN AC7 [get_ports DDR3_DM7]
set_property IOSTANDARD SSTL15 [get_ports DDR3_DM7]
#DQS
set_property PACKAGE_PIN AC15 [get_ports DDR3_DQS0_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS0_N]
set_property PACKAGE_PIN AC16 [get_ports DDR3_DQS0_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS0_P]
set_property PACKAGE_PIN Y18 [get_ports DDR3_DQS1_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS1_N]
set_property PACKAGE_PIN Y19 [get_ports DDR3_DQS1_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS1_P]
set_property PACKAGE_PIN AK18 [get_ports DDR3_DQS2_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS2_N]
set_property PACKAGE_PIN AJ18 [get_ports DDR3_DQS2_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS2_P]
set_property PACKAGE_PIN AJ16 [get_ports DDR3_DQS3_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS3_N]
set_property PACKAGE_PIN AH16 [get_ports DDR3_DQS3_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS3_P]
set_property PACKAGE_PIN AJ7 [get_ports DDR3_DQS4_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS4_N]
set_property PACKAGE_PIN AH7 [get_ports DDR3_DQS4_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS4_P]
set_property PACKAGE_PIN AH1 [get_ports DDR3_DQS5_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS5_N]
set_property PACKAGE_PIN AG2 [get_ports DDR3_DQS5_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS5_P]
set_property PACKAGE_PIN AG3 [get_ports DDR3_DQS6_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS6_N]
set_property PACKAGE_PIN AG4 [get_ports DDR3_DQS6_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS6_P]
set_property PACKAGE_PIN AD1 [get_ports DDR3_DQS7_N]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS7_N]
set_property PACKAGE_PIN AD2 [get_ports DDR3_DQS7_P]
set_property IOSTANDARD DIFF_SSTL15 [get_ports DDR3_DQS7_P]
#BPI FLASH
#DATA
set_property PACKAGE_PIN P24 [get_ports FLASH_D0]
set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D0]
set_property PACKAGE_PIN R25 [get_ports FLASH_D1]
set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D1]
set_property PACKAGE_PIN R20 [get_ports FLASH_D2]
set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D2]
set_property PACKAGE_PIN R21 [get_ports FLASH_D3]
set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D3]
set_property PACKAGE_PIN T20 [get_ports FLASH_D4]
set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D4]
set_property PACKAGE_PIN T21 [get_ports FLASH_D5]
set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D5]
set_property PACKAGE_PIN T22 [get_ports FLASH_D6]
set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D6]
set_property PACKAGE_PIN T23 [get_ports FLASH_D7]
set_property IOSTANDARD LVCMOS25 [get_ports FLASH_D7]
set_property PACKAGE_PIN U20 [get_ports FLASH_D8]
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Xilinx KC705 Specifications

General

Brand	Xilinx
Model	KC705
Category	Motherboard
Language	English