Xilinx KCU105 User Manual

KCU105 Board User Guide www.xilinx.com 29
UG917 (v1.4) September 25, 2015
Chapter 1: KCU105 Evaluation Board Features
Tab le 1- 7 lists the source devices for each clock.
Table 1-7: KCU105 Board Clock Sources
Clock Name Clock Ref. Des. Description
System Clock 300 MHz U122
• Silicon Labs Si5335A 1.8V LVDS Any Frequency Quad
Clock Generator CLK0.
•See Clock Generation (SYSCLK_300_P and
SYSCLK_300_N).
System Clock 125 MHz U122
• Silicon Labs Si5335A 1.8V LVDS Any Frequency Quad
Clock Generator CLK1.
•See Clock Generation (CLK_125MHZ).
EMC Clock 90 MHz U122
• Silicon Labs Si5335A 1.8V LVCMOS Single-Ended Any
Frequency Quad Clock Generator CLK2.
•See Clock Generation (FPGA_EMCCLK).
System Ctlr. Clock
33.333 MHz
U122
• Silicon Labs Si5335A 1.8V LVCMOS single-ended any
frequency quad clock generator CLK3.
•See Clock Generation (SYSCTLR_CLK).
User Clock
10MHz-810 MHz
U32
• Silicon Labs Si570 3.3V LVDS I2C programmable
oscillator, 156.250 MHz default. Available from the
output Q0 of Silicon Labs Si53340 clock buffer.
•See Programmable User Clock Source
(USER_SI570_CLOCK_P and USER_SI570_CLOCK_N).
GTH SMA REF Clock J33(P), J32(N)
• User clock input SMAs.
•See GTH TX and RX SMA Differential Pairs
(SMA_MGT_REFCLK_P and SMA_MGT_REFCLK_N).
User SMA Clock J34(P), J35(N)
• User clock input SMAs.
•See User SMA Clock Input (USER_SMA_CLOCK_P and
USER_SMA_CLOCK_N).
Jitter Attenuated Clock
CKOUT1
U57
• Silicon Labs Si5328B LVDS precision clock
multiplier/jitter attenuator.
•See Jitter Attenuated Clock (SI5328_OUT_P and
SI5328_OUT_N).
Jitter Attenuated Clock
CKOUT2
U57
• Silicon Labs Si5328B LVDS precision clock
multiplier/jitter attenuator.
•See Jitter Attenuated Clock (SI5328_OUT2_P and
SI5328_OUT2_N).
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Xilinx KCU105 Specifications

General

Brand	Xilinx
Model	KCU105
Category	Motherboard
Language	English