Xilinx RocketIO User Manual

100 www.xilinx.com RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
Chapter 2: Digital Design Considerations
R
-- is, upon an asserted RXREALIGN
-- or RXCOMMADET.
PROCESS (usrclk2)
BEGIN
IF (usrclk2'EVENT AND usrclk2 = '1') THEN
IF (rxreset = '1') THEN
wait_to_sync <= “1111”;
count <= '0';
ELSE
IF (rxrealign = '1') THEN
wait_to_sync <= “1111”;
count <= '1';
ELSE
IF (count = '1') THEN
IF (wait_to_sync /= “0000”) THEN
wait_to_sync <= wait_to_sync - “0001”;
END IF;
END IF;
IF (rxcommadet = '1') THEN
count <= '1';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- This process maintains output sync, which
-- indicates when outgoing aligned_data
-- should be properly aligned, with the comma
-- in aligned_data[31:24]. Output aligned_data is
-- considered to be in sync when a comma is seen
-- on rxdata (as indicated
-- by rxchariscomma3 or 1) after the counter
-- wait_to_sync has reached 0, indicating
-- that commas seen by the comma detection circuit
-- have had time to propagate to
-- aligned_data after initialization of the elastic buffer.
PROCESS (usrclk2)
BEGIN
IF (usrclk2'EVENT AND usrclk2 = '1') THEN
IF ((rxreset OR rxrealign) = '1') THEN
sync_hold <= '0';
ELSE
IF (wait_to_sync = “0000”)THEN
IF ((rxchariscomma3 OR rxchariscomma1) = '1') THEN
sync_hold <= '1';
END IF;
END IF;
END IF;
END IF;
END PROCESS;
-- This process generates aligned_data with commas
-- aligned in [31:24],
-- assuming that incoming commas are aligned
-- to [31:24] or [15:8].
-- Here, you could add code to use ENPCOMMAALIGN and
-- ENMCOMMAALIGN to enable a move back into the
Product Not Recommended for New Designs

Xilinx RocketIO Specifications

General

Form Factor	Integrated into Xilinx FPGAs and SoCs
Technology	CMOS
Category	Transceiver
Protocol Support	Aurora, Ethernet, CPRI
Package	Integrated into FPGA/SoC package
Data Rate	Up to 28.05 Gbps
Signal Integrity	Integrated equalization, pre-emphasis, and decision feedback equalization (DFE)

Summary

Chapter 1: RocketIO Transceiver Overview

Basic Architecture and Capabilities

List of Available Ports

Chapter 2: Digital Design Considerations

Clocking

BREFCLK

Digital Clock Manager (DCM) Examples

Half-Rate Clocking Scheme

RXRECCLK

Data Path Latency

Reset/Power Down

8B/10B Encoding/Decoding

SERDES Alignment

Explains SERDES alignment for serial data transmission and reception.

ENPCOMMAALIGN, ENMCOMMAALIGN

Clock Recovery

Introduces clock/data recovery circuits for synchronous serial data reception.

Clock Correction

Synchronization Logic

Explains the importance of knowing data validity and MGT synchronization.

Channel Bonding (Channel Alignment)

Explains channel bonding for aligning multiple transceivers for higher data rates.

CRC (Cyclic Redundancy Check)

Explains CRC as a procedure to detect errors in received data.

Fabric Interface (Buffers)

Explains the reasons for including buffers in transmit and receive paths.

Chapter 3: Analog Design Considerations

Serial I/O Description

Pre-emphasis Techniques

Explains techniques to boost voltage swing for signal integrity over lossy media.

Differential Receiver

Describes the differential receiver's input and parameters.

Jitter

Clock and Data Recovery

Explains the CDR function for locking to input data streams and deriving clocks.

PCB Design Requirements

Outlines requirements for reliable RocketIO transceiver operation.

Power Conditioning

Details requirements for power filtering and noise isolation for transceiver pins.

Voltage Regulator Selection and Use

Provides criteria for selecting linear regulators for RocketIO transceiver supplies.

Passive Filtering

Explains the need for passive filter networks on power supply pins for noise isolation.

High-Speed Serial Trace Design

Provides guidelines for routing high-speed serial traces on PCBs.

Differential Trace Design

Details trace geometry and spacing for achieving required differential impedance.

AC and DC Coupling

Explains when to use AC or DC coupling for transceiver signal paths.

Reference Clock

Specifies requirements for accurate reference clocks for transceiver operation.

Other Important Design Notes

Powering the RocketIO Transceivers

Emphasizes connecting all transceivers to power and ground, even unused ones.

The POWERDOWN Port

Chapter 4: Simulation and Implementation

Simulation Models

MGT Package Pins

Details package pin assignments for MGTs and their correlation to LOC constraints.

Appendix A: RocketIO Transceiver Timing Model

Timing Parameters

Explains the designations of timing parameters used in tables.

Setup/Hold Times of Inputs Relative to Clock

Clock to Output Delays

Clock Pulse Width

Appendix B: 8B/10B Valid Characters

Valid Data Characters

Valid Control Characters (K-Characters)

Appendix C: Related Online Documents

Application Notes

Virtex-II Pro RocketIO Multi-Gigabit Transceiver Characterization Summary