Xilinx RocketIO - Page 101

RocketIO™ Transceiver User Guide www.xilinx.com 101
UG024 (v3.0) February 22, 2007
Other Important Design Notes
R
-- byte_sync=0 state.
PROCESS (usrclk2, rxreset)
BEGIN
IF (rxreset = '1') THEN
rxdata_reg <= “0000000000000000”;
rxdata_hold <= “00000000000000000000000000000000”;
rxisk_reg <= “00”;
rxisk_hold <= “0000”;
byte_sync <= '0';
ELSIF (usrclk2'EVENT AND usrclk2 = '1') THEN
rxdata_reg(15 DOWNTO 0) <= rxdata(15 DOWNTO 0);
rxisk_reg(1 DOWNTO 0) <= rxisk(1 DOWNTO 0);
IF (rxchariscomma3 = '1') THEN
rxdata_hold(31 DOWNTO 0) <= rxdata(31 DOWNTO 0);
rxisk_hold(3 DOWNTO 0) <= rxisk(3 DOWNTO 0);
byte_sync <= '0';
ELSE
IF ((rxchariscomma1 OR byte_sync) = '1') THEN
rxdata_hold(31 DOWNTO 0) <= rxdata_reg(15 DOWNTO 0) &
rxdata(31 DOWNTO 16);
rxisk_hold(3 DOWNTO 0) <= rxisk_reg(1 DOWNTO 0) &
rxisk(3 DOWNTO 2);
byte_sync <= '1';
ELSE
rxdata_hold(31 DOWNTO 0) <= rxdata(31 DOWNTO 0);
rxisk_hold(3 DOWNTO 0) <= rxisk(3 DOWNTO 0);
END IF;
END IF;
END IF;
END PROCESS;
END ARCHITECTURE translated;
Product Not Recommended for New Designs