Xilinx RocketIO User Manual

30 www.xilinx.com RocketIO™ Transceiver User Guide
UG024 (v3.0) February 22, 2007
Chapter 1: RocketIO Transceiver Overview
R
CHAN_BOND_OFFSET Integer 0-15 that defines offset (in bytes) from channel bonding sequence for
realignment. It specifies the first elastic buffer read address that all channel-
bonded transceivers have immediately after channel bonding.
CHAN_BOND_WAIT specifies the number of bytes that the master
transceiver passes to RXDATA, starting with the channel bonding sequence,
before the transceiver executes channel bonding (alignment) across all
channel-bonded transceivers.
CHAN_BOND_OFFSET specifies the first elastic buffer read address that all
channel-bonded transceivers have immediately after channel bonding
(alignment), as a positive offset from the beginning of the matched channel
bonding sequence in each transceiver.
For optimal performance of the elastic buffer, CHAN_BOND_WAIT and
CHAN_BOND_OFFSET should be set to the same value (typically 8).
CHAN_BOND_ONE_SHOT TRUE/FALSE that controls repeated execution of channel bonding.
FALSE: Master transceiver initiates channel bonding whenever possible
(whenever channel-bonding sequence is detected in the input) as long as
input ENCHANSYNC is High and RXRESET is Low.
TRUE: Master transceiver initiates channel bonding only the first time it
is possible (channel bonding sequence is detected in input) following
negated RXRESET and asserted ENCHANSYNC. After channel-bonding
alignment is done, it does not occur again until RXRESET is asserted and
negated, or until ENCHANSYNC is negated and reasserted.
Always set Slave transceivers CHAN_BOND_ONE_SHOT to FALSE.
CHAN_BOND_SEQ_*_* 11-bit vectors that define the channel bonding sequence. The usage of these
vectors also depends on CHAN_BOND_SEQ_LEN and
CHAN_BOND_SEQ_2_USE. See “Receiving Vitesse Channel Bonding
Sequence,” page 65, for format.
CHAN_BOND_SEQ_2_USE Controls use of second channel bonding sequence.
FALSE: Channel bonding uses only one channel bonding sequence
defined by CHAN_BOND_SEQ_1_1...4.
TRUE: Channel bonding uses two channel bonding sequences defined
by:
CHAN_BOND_SEQ_1_1...4 and
CHAN_BOND_SEQ_2_1...4
as further constrained by CHAN_BOND_SEQ_LEN.
CHAN_BOND_SEQ_LEN Integer 1-4 defines length in bytes of channel bonding sequence. This
defines the length of the sequence the transceiver matches to detect
opportunities for channel bonding.
CHAN_BOND_WAIT Integer 1-15 that defines the length of wait (in bytes) after seeing channel
bonding sequence before executing channel bonding.
Table 1-6: RocketIO Transceiver Attributes (Continued)
Attribute Description
Product Not Recommended for New Designs

Xilinx RocketIO Specifications

General

Form Factor	Integrated into Xilinx FPGAs and SoCs
Technology	CMOS
Category	Transceiver
Protocol Support	Aurora, Ethernet, CPRI
Package	Integrated into FPGA/SoC package
Data Rate	Up to 28.05 Gbps
Signal Integrity	Integrated equalization, pre-emphasis, and decision feedback equalization (DFE)

Summary

Chapter 1: RocketIO Transceiver Overview

Basic Architecture and Capabilities

List of Available Ports

Chapter 2: Digital Design Considerations

Clocking

BREFCLK

Digital Clock Manager (DCM) Examples

Half-Rate Clocking Scheme

RXRECCLK

Data Path Latency

Reset/Power Down

8B/10B Encoding/Decoding

SERDES Alignment

Explains SERDES alignment for serial data transmission and reception.

ENPCOMMAALIGN, ENMCOMMAALIGN

Clock Recovery

Introduces clock/data recovery circuits for synchronous serial data reception.

Clock Correction

Synchronization Logic

Explains the importance of knowing data validity and MGT synchronization.

Channel Bonding (Channel Alignment)

Explains channel bonding for aligning multiple transceivers for higher data rates.

CRC (Cyclic Redundancy Check)

Explains CRC as a procedure to detect errors in received data.

Fabric Interface (Buffers)

Explains the reasons for including buffers in transmit and receive paths.

Chapter 3: Analog Design Considerations

Serial I/O Description

Pre-emphasis Techniques

Explains techniques to boost voltage swing for signal integrity over lossy media.

Differential Receiver

Describes the differential receiver's input and parameters.

Jitter

Clock and Data Recovery

Explains the CDR function for locking to input data streams and deriving clocks.

PCB Design Requirements

Outlines requirements for reliable RocketIO transceiver operation.

Power Conditioning

Details requirements for power filtering and noise isolation for transceiver pins.

Voltage Regulator Selection and Use

Provides criteria for selecting linear regulators for RocketIO transceiver supplies.

Passive Filtering

Explains the need for passive filter networks on power supply pins for noise isolation.

High-Speed Serial Trace Design

Provides guidelines for routing high-speed serial traces on PCBs.

Differential Trace Design

Details trace geometry and spacing for achieving required differential impedance.

AC and DC Coupling

Explains when to use AC or DC coupling for transceiver signal paths.

Reference Clock

Specifies requirements for accurate reference clocks for transceiver operation.

Other Important Design Notes

Powering the RocketIO Transceivers

Emphasizes connecting all transceivers to power and ground, even unused ones.

The POWERDOWN Port

Chapter 4: Simulation and Implementation

Simulation Models

MGT Package Pins

Details package pin assignments for MGTs and their correlation to LOC constraints.

Appendix A: RocketIO Transceiver Timing Model

Timing Parameters

Explains the designations of timing parameters used in tables.

Setup/Hold Times of Inputs Relative to Clock

Clock to Output Delays

Clock Pulse Width

Appendix B: 8B/10B Valid Characters

Valid Data Characters

Valid Control Characters (K-Characters)

Appendix C: Related Online Documents

Application Notes

Virtex-II Pro RocketIO Multi-Gigabit Transceiver Characterization Summary