Xilinx RocketIO User Manual

RocketIO™ Transceiver User Guide www.xilinx.com 31
UG024 (v3.0) February 22, 2007
Primitive Attributes
R
CLK_COR_INSERT_IDLE_FLAG TRUE/FALSE controls whether RXRUNDISP input status denotes running
disparity or inserted-idle flag.
FALSE: RXRUNDISP denotes running disparity when RXDATA is
decoded data.
TRUE: RXRUNDISP is raised for the first byte of each inserted (repeated)
clock correction (“Idle”) sequence (when RXDATA is decoded data).
CLK_COR_KEEP_IDLE TRUE/FALSE controls whether or not the final byte stream must retain at
least one clock correction sequence.
FALSE: Transceiver can remove all clock correction sequences to further
recenter the elastic buffer during clock correction.
TRUE: In the final RXDATA stream, the transceiver must leave at least
one clock correction sequence per continuous stream of clock correction
sequences.
CLK_COR_REPEAT_WAIT Integer 0 - 31 controls frequency of repetition of clock correction operations.
This attribute specifies the minimum number of RXUSRCLK cycles without
clock correction that must occur between successive clock corrections. If this
attribute is zero, no limit is placed on how frequently clock correction can
occur.
CLK_COR_SEQ_*_* 11-bit vectors that define the sequence for clock correction. The attribute
used depends on the CLK_COR_SEQ_LEN and CLK_COR_SEQ_2_USE.
CLK_COR_SEQ_2_USE TRUE/FALSE controls use of second clock correction sequence.
FALSE: Clock correction uses only one clock correction sequence defined
by CLK_COR_SEQ_1_1...4.
TRUE: Clock correction uses two clock correction sequences defined by:
CLK_COR_SEQ_1_1...4 and
CLK_COR_SEQ_2_1...4
as further constrained by CLK_COR_SEQ_LEN.
CLK_COR_SEQ_LEN Integer that defines the length of the sequence the transceiver matches to
detect opportunities for clock correction. It also defines the size of the
correction, since the transceiver executes clock correction by repeating or
skipping entire clock correction sequences.
CLK_CORRECT_USE TRUE/FALSE controls the use of clock correction logic.
FALSE: Permanently disable execution of clock correction (rate
matching). Clock RXUSRCLK must be frequency-locked with
RXRECCLK in this case.
TRUE: Enable clock correction (normal mode).
COMMA_10B_MASK This 10-bit vector defines the mask that is ANDed with the incoming serial
bit stream before comparison against PCOMMA_10B_VALUE and
MCOMMA_10B_VALUE.
Table 1-6: RocketIO Transceiver Attributes (Continued)
Attribute Description
Product Not Recommended for New Designs

Xilinx RocketIO Specifications

General

Brand	Xilinx
Model	RocketIO
Category	Transceiver
Language	English