Xilinx VCU118 User Manual

VCU118 Board User Guide 25
UG1224 (v1.0) December 15, 2016
www.xilinx.com
Chapter 3: Board Component Descriptions
C23 DDR4_C1_DQ67 POD12_DCI H7 DQL3 U64
B23 DDR4_C1_DQ68 POD12_DCI H2 DQL4 U64
B22 DDR4_C1_DQ69 POD12_DCI H8 DQL5 U64
B21 DDR4_C1_DQ70 POD12_DCI J3 DQL6 U64
A21 DDR4_C1_DQ71 POD12_DCI J7 DQL7 U64
D7 DDR4_C1_DQ72 POD12_DCI A3 DQU0 U64
C7 DDR4_C1_DQ73 POD12_DCI B8 DQU1 U64
B8 DDR4_C1_DQ74 POD12_DCI C3 DQU2 U64
B7 DDR4_C1_DQ75 POD12_DCI C7 DQU3 U64
C10 DDR4_C1_DQ76 POD12_DCI C2 DQU4 U64
B10 DDR4_C1_DQ77 POD12_DCI C8 DQU5 U64
B11 DDR4_C1_DQ78 POD12_DCI D3 DQU6 U64
A11 DDR4_C1_DQ79 POD12_DCI D7 DQU7 U64
D22 DDR4_C1_DQS8_T DIFF_POD12_DCI G3 DQSL_T U64
C22 DDR4_C1_DQS8_C DIFF_POD12_DCI F3 DQSL_C U64
A9 DDR4_C1_DQS9_T DIFF_POD12_DCI B7 DQSU_T U64
A8 DDR4_C1_DQS9_C DIFF_POD12_DCI A7 DQSU_C U64
E24 DDR4_C1_DM8 POD12_DCI E7 DML_B/DBIL_B U64
C9 DDR4_C1_DM9 POD12_DCI E2 DMU_B/DBIU_B U64
D14 DDR4_C1_A0 SSTL12_DCI P3 A0 U60-U64
B15 DDR4_C1_A1 SSTL12_DCI P7 A1 U60-U64
B16 DDR4_C1_A2 SSTL12_DCI R3 A2 U60-U64
C14 DDR4_C1_A3 SSTL12_DCI N7 A3 U60-U64
C15 DDR4_C1_A4 SSTL12_DCI N3 A4 U60-U64
A13 DDR4_C1_A5 SSTL12_DCI P8 A5 U60-U64
A14 DDR4_C1_A6 SSTL12_DCI P2 A6 U60-U64
A15 DDR4_C1_A7 SSTL12_DCI R8 A7 U60-U64
A16 DDR4_C1_A8 SSTL12_DCI R2 A8 U60-U64
B12 DDR4_C1_A9 SSTL12_DCI R7 A9 U60-U64
C12 DDR4_C1_A10 SSTL12_DCI M3 A10/AP U60-U64
B13 DDR4_C1_A11 SSTL12_DCI T2 A11 U60-U64
C13 DDR4_C1_A12 SSTL12_DCI M7 A12/BC_B U60-U64
D15 DDR4_C1_A13 SSTL12_DCI T8 A13 U60-U64
G15 DDR4_C1_BA0 SSTL12_DCI N2 BA0 U60-U64
Table 3-2: DDR4 Memory 80-bit I/F C1 to FPGA U1 Banks 71, 72, and 73 (Cont’d)
FPGA (U1)
Pin
Schematic Net Name I/O Standard
Component Memory
Pin # Pin Name Ref. Des.
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Xilinx VCU118 Specifications

General

Brand	Xilinx
Model	VCU118
Category	Motherboard
Language	English