Xilinx Virtex-5 FPGA ML561 User Manual

Virtex-5 FPGA ML561 User Guide www.xilinx.com 77
UG199 (v1.2.1) June 15, 2009
Signal Integrity Correlation Results
R
Figure 7-31: DDR2 DIMM Read HW Measurement - Eye Scope Shot at Probe Point (FPGA1 Via)
UG199_c7_31_071107
Figure 7-32: DDR2 DIMM Read Correlation - Eye Scope Shot at Probe Point (Slow Corner)
2000.0 2400.0 2800.0 3200.0 3600.0
-100.0
100.0
300.0
500.0
700.0
900.0
1100.0
1300.0
1500.0
1700.0
1900.0
Time (ps)
Voltage (mV)
UG199_c7_32_071107
Probe 3:C8.1 (at pin)
♦ 333 MHz, Slow, PRBS6, 59% UI
♦ Cursor 1: 1.0988V, 2.5207 ns
♦ Cursor 2: 1.0254V, 3.3859 ns
♦ Delta Voltage = 73.4 mV, Delta Time = 865.2 ps (59% UI)

Xilinx Virtex-5 FPGA ML561 Specifications

General

Brand	Xilinx
Model	Virtex-5 FPGA ML561
Category	Motherboard
Language	English