Xilinx Virtex-7 FPGA VC7222 IBERT - Page 47

VC7222 IBERT Getting Started Guide www.xilinx.com 47
UG971 (v5.0) June 12, 2014
9. In the Clock Settings tab, select DIFF SSTL15 for the I/O Standard, enter AL24 for P
Package Pin and AL25 for N Package Pin (the FPGA pins that the system clock
connects to), and ensure the Frequency is set to 200.00 (Figure 2-7). Click OK. Click
Generate in the next window to generate the output products.
X-Ref Target - Figure 2-7
Figure 2-7: Customize IP - Clock Settings
8*BFBB
Send Feedback