Xilinx Virtex-7 FPGA VC7222 IBERT - Page 48

48 www.xilinx.com VC7222 IBERT Getting Started Guide
UG971 (v5.0) June 12, 2014
Chapter 2: Creating the GTH IBERT Core
10. In the Manage IP window (Figure 2-3), in the Sources window, right-click the IBERT
IP and select Open IP Example Design (Figure 2-8). Specify a location to save the
design, press OK, and the design opens in a new Vivado window.
X-Ref Target - Figure 2-8
Figure 2-8: Open IP Example Design
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