Xilinx ZCU102 User Manual

ZCU102 Evaluation Board User Guide www.xilinx.com 124
UG1182 (v1.2) March 20, 2017
Appendix B: Master Constraints File Listing
set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA27_P"]
set_property PACKAGE_PIN T6 [get_ports "FMC_HPC0_LA28_N"]
set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA28_N"]
set_property PACKAGE_PIN T7 [get_ports "FMC_HPC0_LA28_P"]
set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA28_P"]
set_property PACKAGE_PIN U8 [get_ports "FMC_HPC0_LA29_N"]
set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA29_N"]
set_property PACKAGE_PIN U9 [get_ports "FMC_HPC0_LA29_P"]
set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA29_P"]
set_property PACKAGE_PIN U6 [get_ports "FMC_HPC0_LA30_N"]
set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA30_N"]
set_property PACKAGE_PIN V6 [get_ports "FMC_HPC0_LA30_P"]
set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA30_P"]
set_property PACKAGE_PIN V7 [get_ports "FMC_HPC0_LA31_N"]
set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA31_N"]
set_property PACKAGE_PIN V8 [get_ports "FMC_HPC0_LA31_P"]
set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA31_P"]
set_property PACKAGE_PIN T11 [get_ports "FMC_HPC0_LA32_N"]
set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA32_N"]
set_property PACKAGE_PIN U11 [get_ports "FMC_HPC0_LA32_P"]
set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA32_P"]
set_property PACKAGE_PIN V11 [get_ports "FMC_HPC0_LA33_N"]
set_property IOSTANDARD LVCMOS18 [get_ports "FMC_HPC0_LA33_N"]
set_property PACKAGE_PIN V12 [get_ports "FMC_HPC0_LA33_P"]
#HPC1 J4
set_property PACKAGE_PIN AF7 [get_ports "FMC_HPC1_CLK0_M2C_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_CLK0_M2C_N"]
set_property PACKAGE_PIN AE7 [get_ports "FMC_HPC1_CLK0_M2C_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_CLK0_M2C_P"]
set_property PACKAGE_PIN P9 [get_ports "FMC_HPC1_CLK1_M2C_N"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_CLK1_M2C_N"]
set_property PACKAGE_PIN P10 [get_ports "FMC_HPC1_CLK1_M2C_P"]
set_property IOSTANDARD LVDS [get_ports "FMC_HPC1_CLK1_M2C_P"]
set_property PACKAGE_PIN G28 [get_ports "FMC_HPC1_GBTCLK0_M2C_C_N"]
set_property PACKAGE_PIN G27 [get_ports "FMC_HPC1_GBTCLK0_M2C_C_P"]
set_property PACKAGE_PIN E28 [get_ports "FMC_HPC1_GBTCLK1_M2C_C_N"]
set_property PACKAGE_PIN E27 [get_ports "FMC_HPC1_GBTCLK1_M2C_C_P"]
set_property PACKAGE_PIN F30 [get_ports "FMC_HPC1_DP0_C2M_N"]
set_property PACKAGE_PIN F29 [get_ports "FMC_HPC1_DP0_C2M_P"]
set_property PACKAGE_PIN E32 [get_ports "FMC_HPC1_DP0_M2C_N"]
set_property PACKAGE_PIN E31 [get_ports "FMC_HPC1_DP0_M2C_P"]
set_property PACKAGE_PIN D30 [get_ports "FMC_HPC1_DP1_C2M_N"]
set_property PACKAGE_PIN D29 [get_ports "FMC_HPC1_DP1_C2M_P"]
set_property PACKAGE_PIN D34 [get_ports "FMC_HPC1_DP1_M2C_N"]
set_property PACKAGE_PIN D33 [get_ports "FMC_HPC1_DP1_M2C_P"]
set_property PACKAGE_PIN B30 [get_ports "FMC_HPC1_DP2_C2M_N"]
set_property PACKAGE_PIN B29 [get_ports "FMC_HPC1_DP2_C2M_P"]
set_property PACKAGE_PIN C32 [get_ports "FMC_HPC1_DP2_M2C_N"]
set_property PACKAGE_PIN C31 [get_ports "FMC_HPC1_DP2_M2C_P"]
set_property PACKAGE_PIN A32 [get_ports "FMC_HPC1_DP3_C2M_N"]
set_property PACKAGE_PIN A31 [get_ports "FMC_HPC1_DP3_C2M_P"]
set_property PACKAGE_PIN B34 [get_ports "FMC_HPC1_DP3_M2C_N"]
set_property PACKAGE_PIN B33 [get_ports "FMC_HPC1_DP3_M2C_P"]
set_property PACKAGE_PIN K30 [get_ports "FMC_HPC1_DP4_C2M_N"]
set_property PACKAGE_PIN K29 [get_ports "FMC_HPC1_DP4_C2M_P"]
set_property PACKAGE_PIN L32 [get_ports "FMC_HPC1_DP4_M2C_N"]
set_property PACKAGE_PIN L31 [get_ports "FMC_HPC1_DP4_M2C_P"]
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Xilinx ZCU102 Specifications

General

Processor	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
SD Card	MicroSD card slot
Video Outputs	DisplayPort
FPGA	Xilinx Zynq UltraScale+ XCZU9EG-2FFVB1156E
Memory	4GB DDR4 Component Memory
Storage	MicroSD card slot
Ethernet	Gigabit Ethernet
USB	1 x USB 3.0, 1 x USB 2.0
PCIe	PCIe Gen2 x4
Display	DisplayPort
Power Supply	12V DC input
SATA	SATA 3.0
Clocking	Programmable clocks
Operating System Support	PetaLinux