Xilinx ZCU102 User Manual

ZCU102 Evaluation Board User Guide www.xilinx.com 21
UG1182 (v1.2) March 20, 2017
Chapter 3: Board Component Descriptions
The top-level block diagram is shown in Figure 3-1.
X-Ref Target - Figure 3-1
Figure 3-1: Zynq UltraScale+ MPSoC Top-Level Block Diagram
RPU
256 KB
OCM
LPD-DMA
CSU
PMU
Processing System
Cortex-R5
32 KB I/D
128 KB TCM
Cortex-R5
32 KB I/D
128 KB TCM
4 x 1GE
APU
Cortex-A53
32 KB I/D
Cortex-A53
32 KB I/D
Cortex-A53
32 KB I/D
Cortex-A53
32 KB I/D
GIC
SCU
ACP 1 MB L2
GPU
Mali-400 MP2
64 KB L2
2 x USB 3.0
NAND x8
ONFI 3.1
2 x SD3.0/
eMMC4.51
Quad-SPI
x 8
2 x SPI
2 x CAN
2 x I2C
2 x UART
GPIOs
SYSMON
MIO
Central
Switch
FPD-DMA
PCIe
Gen4
DisplayPort
v1.2 x1, x2
2 x SATA
v3.1
PCIe Gen2
x1, x2, or x4
SHA3
AES-GCM
RSA
Processor
System
BPU
DDRC (DDR4/3/3L, LPDDR3/4)
Programmable
Logic
128 KB RAM
PL_LPD
HP
GIC
RGMII
ULPI
PS-GTR
SMMU/CCI
GFC
USB 3.0
SGMII
Low Power Switch
To ACP
Low Power Full Power
Battery
Power
32-bit/64-bit
64-bit
MS
128-bit
MS
LPD_PL HPCHPM
GTY
Quad
GTH
Quad
Interlaken
100G
Ethernet
ACE
DisplayPort
Video and
Audio Interface
Low-latency
Peripheral Port
Low-latency
Peripheral Port
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Xilinx ZCU102 Specifications

General

Processor	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
SD Card	MicroSD card slot
Video Outputs	DisplayPort
FPGA	Xilinx Zynq UltraScale+ XCZU9EG-2FFVB1156E
Memory	4GB DDR4 Component Memory
Storage	MicroSD card slot
Ethernet	Gigabit Ethernet
USB	1 x USB 3.0, 1 x USB 2.0
PCIe	PCIe Gen2 x4
Display	DisplayPort
Power Supply	12V DC input
SATA	SATA 3.0
Clocking	Programmable clocks
Operating System Support	PetaLinux