Xilinx ZCU102 User Manual

ZCU102 Evaluation Board User Guide www.xilinx.com 84
UG1182 (v1.2) March 20, 2017
Chapter 3: Board Component Descriptions
Table 3-36 lists GTH bank 129 connections.
Table 3-36: ZCU102 GTH Bank 129 Interface Connections
XCZU9EG
(U1) Pin
XCZU9EG (U1) Pin
Name
Schematic Net Name
(2)
Connected To
Pin No. Pin Name Device
K29
MGTHTXP0_129 FMC_HPC1_DP4_C2M_P
A34
DP4_C2M_P
FMC HPC1 J4
K30
MGTHTXN0_129 FMC_HPC1_DP4_C2M_N
A35
DP4_C2M_N
L31
MGTHRXP0_129 FMC_HPC1_DP4_M2C_P
A14
DP4_M2C_P
L32
MGTHRXN0_129 FMC_HPC1_DP4_M2C_N
A15
DP4_M2C_N
J31
MGTHTXP1_129 FMC_HPC1_DP5_C2M_P
A38
DP5_C2M_P
J32
MGTHTXN1_129 FMC_HPC1_DP5_C2M_N
A39
DP5_C2M_N
K33
MGTHRXP1_129 FMC_HPC1_DP5_M2C_P
A18
DP5_M2C_P
K34
MGTHRXN1_129 FMC_HPC1_DP5_M2C_N
A19
DP5_M2C_N
H29
MGTHTXP2_129 FMC_HPC1_DP6_C2M_P
B36
DP6_C2M_P
H30
MGTHTXN2_129 FMC_HPC1_DP6_C2M_N
B37
DP6_C2M_N
H33
MGTHRXP2_129 FMC_HPC1_DP6_M2C_P
B16
DP6_M2C_P
H34
MGTHRXN2_129 FMC_HPC1_DP6_M2C_N
B17
DP6_M2C_N
G31
MGTHTXP3_129 FMC_HPC1_DP7_C2M_P
B32
DP7_C2M_P
G32
MGTHTXN3_129 FMC_HPC1_DP7_C2M_N
B33
DP7_C2M_N
F33
MGTHRXP3_129 FMC_HPC1_DP7_M2C_P
B12
DP7_M2C_P
F34
MGTHRXN3_129 FMC_HPC1_DP7_M2C_N
B13
DP7_M2C_N
L27
MGTREFCLK0P_129 USER_MGT_SI570_CLOCK1_C_P
(1)
11
Q1_P
SI53340
(3)
BUFF. U51
L28
MGTREFCLK0N_129 USER_MGT_SI570_CLOCK1_C_N
(1)
12
Q1_N
J27
MGTREFCLK1P_129 USER_SMA_MGT_CLOCK_C_P
(1)
1
SIG J79
J28 MGTREFCLK1N_129 USER_SMA_MGT_CLOCK_C_N
(1)
1SIG J80
Notes:
1. Series capacitor coupled.
2. MGT connections I/O standard not applicable.
3. U51 buffer driven by SI570 U56 (156.250 MHz default)
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Xilinx ZCU102 Specifications

General

Processor	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
SD Card	MicroSD card slot
Video Outputs	DisplayPort
FPGA	Xilinx Zynq UltraScale+ XCZU9EG-2FFVB1156E
Memory	4GB DDR4 Component Memory
Storage	MicroSD card slot
Ethernet	Gigabit Ethernet
USB	1 x USB 3.0, 1 x USB 2.0
PCIe	PCIe Gen2 x4
Display	DisplayPort
Power Supply	12V DC input
SATA	SATA 3.0
Clocking	Programmable clocks
Operating System Support	PetaLinux