Xilinx ZCU102 User Manual

ZCU102 Evaluation Board User Guide www.xilinx.com 85
UG1182 (v1.2) March 20, 2017
Chapter 3: Board Component Descriptions
Table 3-37 lists GTH bank 130 connections.
Table 3-37: ZCU102 GTH Bank 130 Interface Connections
XCZU9EG
(U1) Pin
XCZU9EG (U1) Pin
Name
Schematic Net Name
(2)
Connected To
Pin No. Pin Name Device
F29
MGTHTXP0_130 FMC_HPC1_DP0_C2M_P
C2
DP0_C2M_P
FMC HPC1 J4
F30
MGTHTXN0_130 FMC_HPC1_DP0_C2M_N
C3
DP0_C2M_N
E31
MGTHRXP0_130 FMC_HPC1_DP0_M2C_P
C6
DP0_M2C_P
E32
MGTHRXN0_130 FMC_HPC1_DP0_M2C_N
C7
DP0_M2C_N
D29
MGTHTXP1_130 FMC_HPC1_DP1_C2M_P
A22
DP1_C2M_P
D30
MGTHTXN1_130 FMC_HPC1_DP1_C2M_N
A23
DP1_C2M_N
D33
MGTHRXP1_130 FMC_HPC1_DP1_M2C_P
A2
DP1_M2C_P
D34
MGTHRXN1_130 FMC_HPC1_DP1_M2C_N
A3
DP1_M2C_N
B29
MGTHTXP2_130 FMC_HPC1_DP2_C2M_P
A26
DP2_C2M_P
B30
MGTHTXN2_130 FMC_HPC1_DP2_C2M_N
A27
DP2_C2M_N
C31
MGTHRXP2_130 FMC_HPC1_DP2_M2C_P
A6
DP2_M2C_P
C32
MGTHRXN2_130 FMC_HPC1_DP2_M2C_N
A7
DP2_M2C_N
A31
MGTHTXP3_130 FMC_HPC1_DP3_C2M_P
A30
DP3_C2M_P
A32
MGTHTXN3_130 FMC_HPC1_DP3_C2M_N
A31
DP3_C2M_N
B33
MGTHRXP3_130 FMC_HPC1_DP3_M2C_P
A10
DP3_M2C_P
B34
MGTHRXN3_130 FMC_HPC1_DP3_M2C_N
A11
DP3_M2C_N
G27
MGTREFCLK0P_130 FMC_HPC1_GBTCLK0_M2C_C_P
(1)
D4
GBTCLK0_M2C_P
G28
MGTREFCLK0N_130 FMC_HPC1_GBTCLK0_M2C_C_N
(1)
D5
GBTCLK0_M2C_N
E27
MGTREFCLK1P_130 FMC_HPC1_GBTCLK1_M2C_C_P
(1)
B20
GBTCLK1_M2C_P
E28
MGTREFCLK1N_130 FMC_HPC1_GBTCLK1_M2C_C_N
(1)
B21
GBTCLK1_M2C_N
Notes:
1. Series capacitor coupled.
2. MGT connections I/O standard not applicable.
Send Feedback

Xilinx ZCU102 Specifications

General

Processor	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
SD Card	MicroSD card slot
Video Outputs	DisplayPort
FPGA	Xilinx Zynq UltraScale+ XCZU9EG-2FFVB1156E
Memory	4GB DDR4 Component Memory
Storage	MicroSD card slot
Ethernet	Gigabit Ethernet
USB	1 x USB 3.0, 1 x USB 2.0
PCIe	PCIe Gen2 x4
Display	DisplayPort
Power Supply	12V DC input
SATA	SATA 3.0
Clocking	Programmable clocks
Operating System Support	PetaLinux