ZCU102 Evaluation Board User Guide www.xilinx.com 88
UG1182 (v1.2) March 20, 2017
Chapter 3: Board Component Descriptions
Table 3-40 lists GTH bank 230 connections.
For additional information on GTH transceivers, see the UltraScale Architecture GTH
Transceivers User Guide (UG576) [Ref 5]. For additional information about UltraScale FPGA
PCIe functionality, see the UltraScale Architecture Gen3 Integrated Block for PCI Express
LogiCORE IP Product Guide (PG156) [Ref 6]. Additional information about the PCI Express
standard is available at the PCI Express website [Ref 19].
Table 3-40: ZCU102 GTH Bank 230 Interface Connections
XCZU9EG
(U1) Pin
XCZU9EG (U1) Pin
Name
Schematic Net Name
(2)
Connected To
Pin No. Pin Name Device
E4
MGTHTXP0_230 SFP0_TX_P
RT18
RT_TD_P
QUAD SFP P2
E3
MGTHTXN0_230 SFP0_TX_N
RT19
RT_TD_N
D2
MGTHRXP0_230 SFP0_RX_P
RT13
RT_RD_P
D1
MGTHRXN0_230 SFP0_RX_N
RT12
RT_RD_N
D6
MGTHTXP1_230 SFP1_TX_P
RL18
RL_TD_P
D5
MGTHTXN1_230 SFP1_TX_N
RL19
RL_TD_N
C4
MGTHRXP1_230 SFP1_RX_P
RL13
RL_RD_P
C3
MGTHRXN1_230 SFP1_RX_N
RL12
RL_RD_N
B6
MGTHTXP2_230 SFP2_TX_P
LT18
LT_TD_P
B5
MGTHTXN2_230 SFP2_TX_N
LT19
LT_TD_N
B2
MGTHRXP2_230 SFP2_RX_P
LT13
LT_RD_P
B1
MGTHRXN2_230 SFP2_RX_N
LT12
LT_RD_N
A8
MGTHTXP3_230 SFP3_TX_P
LL18
LL_TD_P
A7
MGTHTXN3_230 SFP3_TX_N
LL19
LL_TD_N
A4
MGTHRXP3_230 SFP3_RX_P
LL13
LL_RD_P
A3
MGTHRXN3_230 SFP3_RX_N
LL12
LL_RD_N
C8
MGTREFCLK0P_230 USER_MGT_SI570_CLOCK2_C_P
(1)
13
Q2_P
SI53340
(3)
BUFF. U51
C7
MGTREFCLK0N_230 USER_MGT_SI570_CLOCK2_C_N
(1)
14
Q2_N
B10
MGTREFCLK1P_230 SFP_SI5328_OUT_C_P
(1)
28
CLKOUT1_P
SI5328B U20
B9
MGTREFCLK1N_230 SFP_SI5328_OUT_C_N
(1)
29
CLKOUT1_N
Notes:
1. Series capacitor coupled.
2. MGT connections I/O standard not applicable.
3. U51 buffer driven by SI570 U56 (156.250 MHz default).
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