Xilinx ZCU102 User Manual

ZCU102 Evaluation Board User Guide www.xilinx.com 87
UG1182 (v1.2) March 20, 2017
Chapter 3: Board Component Descriptions
Table 3-39 lists GTH bank 229 connections.
Table 3-39: ZCU102 GTH Bank 229 Interface Connections
XCZU9EG
(U1) Pin
XCZU9EG (U1) Pin
Name
Schematic Net Name
(2)
Connected To
Pin No. Pin Name Device
K6
MGTHTXP0_229 FMC_HPC0_DP3_C2M_P
A30
DP3_C2M_P
FMC HPC0 J5
K5
MGTHTXN0_229 FMC_HPC0_DP3_C2M_N
A31
DP3_C2M_N
K2
MGTHRXP0_229 FMC_HPC0_DP3_M2C_P
A10
DP3_M2C_P
K1
MGTHRXN0_229 FMC_HPC0_DP3_M2C_N
A11
DP3_M2C_N
H6
MGTHTXP1_229 FMC_HPC0_DP1_C2M_P
A22
DP1_C2M_P
H5
MGTHTXN1_229 FMC_HPC0_DP1_C2M_N
A23
DP1_C2M_N
J4
MGTHRXP1_229 FMC_HPC0_DP1_M2C_P
A2
DP1_M2C_P
J3
MGTHRXN1_229 FMC_HPC0_DP1_M2C_N
A3
DP1_M2C_N
G4
MGTHTXP2_229 FMC_HPC0_DP0_C2M_P
C2
DP0_C2M_P
G3
MGTHTXN2_229 FMC_HPC0_DP0_C2M_N
C3
DP0_C2M_N
H2
MGTHRXP2_229 FMC_HPC0_DP0_M2C_P
C6
DP0_M2C_P
H1
MGTHRXN2_229 FMC_HPC0_DP0_M2C_N
C7
DP0_M2C_N
F6
MGTHTXP3_229 FMC_HPC0_DP2_C2M_P
A26
DP2_C2M_P
F5
MGTHTXN3_229 FMC_HPC0_DP2_C2M_N
A27
DP2_C2M_N
F2
MGTHRXP3_229 FMC_HPC0_DP2_M2C_P
A6
DP2_M2C_P
F1
MGTHRXN3_229 FMC_HPC0_DP2_M2C_N
A7
DP2_M2C_N
G8
MGTREFCLK0P_229 FMC_HPC0_GBTCLK0_M2C_C_P
(1)
D4
GBTCLK0_M2C_P
G7
MGTREFCLK0N_229 FMC_HPC0_GBTCLK0_M2C_C_N
(1)
D5
GBTCLK0_M2C_N
E8
MGTREFCLK1P_229 NC
NA
NA NA
E7
MGTREFCLK1N_229 NC
NA
NA NA
Notes:
1. Series capacitor coupled.
2. MGT connections I/O standard not applicable.
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Xilinx ZCU102 Specifications

General

Processor	Quad-core ARM Cortex-A53, Dual-core ARM Cortex-R5
SD Card	MicroSD card slot
Video Outputs	DisplayPort
FPGA	Xilinx Zynq UltraScale+ XCZU9EG-2FFVB1156E
Memory	4GB DDR4 Component Memory
Storage	MicroSD card slot
Ethernet	Gigabit Ethernet
USB	1 x USB 3.0, 1 x USB 2.0
PCIe	PCIe Gen2 x4
Display	DisplayPort
Power Supply	12V DC input
SATA	SATA 3.0
Clocking	Programmable clocks
Operating System Support	PetaLinux