ZCU102 Evaluation Board User Guide www.xilinx.com 95
UG1182 (v1.2) March 20, 2017
Chapter 3: Board Component Descriptions
Table 3-45: J5 HPC0 FMC Section C and D Connections to XCZU9EG U1
J5 Pin Schematic Net Name
I/O
Standard
U1 Pin J5 Pin Schematic Net Name
I/O
Standard
U1 Pin
C2 FMC_HPC0_DP0_C2M_P G4 D1 VADJ_FMC_PGOOD
(5)
J4.D1,
U63.32,
U66.6
C3 FMC_HPC0_DP0_C2M_N G3 D4 FMC_HPC0_GBTCLK0_M2C_P
(1)
G8
C6 FMC_HPC0_DP0_M2C_P H2 D5 FMC_HPC0_GBTCLK0_M2C_N
(1)
G7
C7 FMC_HPC0_DP0_M2C_N H1 D8 FMC_HPC0_LA01_CC_P
LVCMOS18 AB4
C10 FMC_HPC0_LA06_P
LVCMOS18
AC2 D9 FMC_HPC0_LA01_CC_N LVCMOS18 AC4
C11 FMC_HPC0_LA06_N
LVCMOS18
AC1 D11 FMC_HPC0_LA05_P LVCMOS18 AB3
C14 FMC_HPC0_LA10_P
LVCMOS18
W5 D12 FMC_HPC0_LA05_N LVCMOS18 AC3
C15 FMC_HPC0_LA10_N
LVCMOS18
W4 D14
FMC_HPC0_LA09_P
LVCMOS18 W2
C18 FMC_HPC0_LA14_P
LVCMOS18
AC7 D15 FMC_HPC0_LA09_N LVCMOS18 W1
C19 FMC_HPC0_LA14_N
LVCMOS18
AC6 D17 FMC_HPC0_LA13_P LVCMOS18 AB8
C22 FMC_HPC0_LA18_CC_P
LVCMOS18
N9 D18 FMC_HPC0_LA13_N LVCMOS18 AC8
C23 FMC_HPC0_LA18_CC_N
LVCMOS18
N8 D20 FMC_HPC0_LA17_CC_P LVCMOS18 P11
C26 FMC_HPC0_LA27_P
LVCMOS18
M10 D21 FMC_HPC0_LA17_CC_N LVCMOS18 N11
C27 FMC_HPC0_LA27_N
LVCMOS18
L10 D23 FMC_HPC0_LA23_P LVCMOS18 L16
C30 FMC_HPC0_IIC_SCL
(2)
D24 FMC_HPC0_LA23_N LVCMOS18 K16
C31 FMC_HPC0_IIC_SDA
(2)
D26 FMC_HPC0_LA26_P LVCMOS18 L15
C34 GND D27 FMC_HPC0_LA26_N
LVCMOS18 K15
C35 VCC12_SW D29 FMC_HPC0_TCK_BUF
(3)
C37 VCC12_SW D30 FPGA_TDO_FMC_TDI_BUF
(4)
C39 UTIL_3V3 D31 FMC_HPC0_TDO_HPC1_TDI
(3)(4)
D32 UTIL_3V3_10A
D33 FMC_HPC0_TMS_BUF (3)
D34 NC
D35 GND
D36 UTIL_3V3
D38 UTIL_3V3
D40 UTIL_3V3
Notes:
1. Series capacitor coupled to XCZU9EG U1 pin.
2. Connected to I2C switch U135 pins 4 and 5.
3. XCZU9EG U1 JTAG TCK, TMS, TDO pins R25, R24, T25 are buffered by U48 SN74AVC8T245.
4. J5 HPC0 TDO-TDI connections to U27 HPC0 FMC JTAG bypass switch (N.C. normally-closed/bypassing J5 until an FMC card
is plugged onto J5).
5. Sourced from VADJ_FMC_BUS voltage regulator U63 MAX15301 pin 32 power good output signal.
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