Xilinx Zynq UltraScale+ ZCU208 - Page 25

Table 6: I/O Voltage Rails (cont'd)
ZU48DR Power Net Name Voltage Connected To
PS Bank 503 VCC1V8 1.8V PS CONFIG I/F
PS Bank 504 VCC1V2 1.2V PS_DDR4_SODIMM (64-BIT) I/F
Notes:
1. The ZCU208 board is shipped with VADJ_FMC set to 1.8V by the MSP430 system controller.
PS DDR4 SODIMM Socket
[Figure 2, callout 2]
The PS-side memory is wired to the Zynq UltraScale+ RFSoC DDRC Bank 504 hard memory
controller. A 64-bit single rank DDR4 SODIMM is inserted into socket J48. The ZCU208 is
shipped with a DDR4 SODIMM installed:
• Manufacturer: Micron
• Part Number: MTA4ATF51264HZ-2G6E1
• Descripon:
○ 4 GByte DDR4 260-Pin SODIMM
○ Single Rank (x 16-bit components)
○ 512 Mb x 64-bit
○ 2666 MT/s
The ZCU208 ZU48DR RFSoC (ZU48DR supports 2400MT/s) PS DDR interface performance is
documented in the Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteriscs
(DS926).
The ZCU208 DDR4 SODIMM interface adheres to the constraints guidelines documented in the
PCB guidelines for DDR4 secon of the UltraScale Architecture PCB Design User Guide (UG583).
The DDR4 SODIMM interface is a 40Ω impedance implementaon. Other memory interface
details are also available in the UltraScale Architecture-Based FPGAs Memory IP LogiCORE IP
Product Guide (PG150).
For addional details, see the Micron MTA4ATF51264HZ-2G6E1 data sheet on the Micron
Technology website.
The detailed RFSoC connecons for the feature described in this secon are documented in the
ZCU208 board XDC le, referenced in Appendix B: Xilinx Design Constraints.
Chapter 3: Board Component Descriptions
UG1410 (v1.0) July 8, 2020 www.xilinx.com
ZCU208 Board User Guide 25
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