ADLINK Technology VPX3-TL BIOS - USB Configuration

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VPX3-TL BIOS
4.2.3 USB Configuration
Aptio Setup – AMI
Chipset
USB Configuration
xDCI Support [Disabled]
USB2 PHY Sus Well Power Gating [Enabled]
USB3 Link Speed Selection [GEN1]
USB PDO Programming [Enabled]
XHCI LTR Mode [Enabled]
USB Overcurrent [Enabled]
USB Overcurrent Lock [Enabled]
><: Select Screen
^v: Select Item
Enter: Select
+/-: Change Opt.
F1: General Help
F8: Previous Values
F9: Optimized Default
F10: Save & Exit
ESC: Exit
BIOS Item Options Description
xDCI Support
Disabled
Enabled
Enable/Disable xDCI (USB OTG Device).
USB2 PHY Sus Well Power
Gating
Disabled
Enabled
Select 'Enabled' to enable SUS Well PG for
USB2 PHY. This option has no effect on
PCH-H
USB3 Link Speed Selection
GEN1
GEN2
This option is to select USB3 Link Speed
GEN1 or GEN2
USB PDO Programming
Disabled
Enabled
Select 'Enabled' if Port Disable Override
functionality is used.
XHCI LTR Mode
Disabled
Enabled
Enable/Disable XHCI LTR Mode
USB Overcurrent
Disabled
Enabled
Select 'Disabled' for pin-based debug. If
pin-based debug is enabled but USB
overcurrent is not disabled, USB DbC does
not work.
USB Overcurrent Lock
Disabled
Enabled
Select 'Enabled' if Overcurrent
functionality is used. Enabling this will
make xHCI controller consume the
Overcurrent mapping data