Alinx AX7021 - Clock Configuration

ZYNQ FPGA Development Board AX7021 User Manual
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Pin Assignment of eMMC Flash
Signal Name
ZYNQ Pin Name
Pin Number
MMC_CCLK
PS_MIO48_501
D11
MMC_CMD
PS_MIO47_501
B10
MMC_D0
PS_MIO46_501
D12
MMC_D1
PS_MIO49_501
C14
MMC_D2
PS_MIO50_501
D13
MMC_D3
PS_MIO51_501
C10
Table 2-5-2: Pin Assignment of eMMC FLASH
2.6 Clock configuration
The AC7021 core board provides active clocks for the PS system and the
PL logic sections, respectively, so that the PS system and the PL logic can
work independently.
PS system clock source
The ZYNQ chip provides a 33.333 MHz clock input to the PS section
through the X1 crystal on the development board. The input of the clock is
connected to the pins of PS_CLK_500 of the BANK500 of the ZYNQ chip. The
schematic diagram is shown in Figure 2-6-1:
Figure 2-6-1: Active crystal oscillator to the PS section
Figure 2-6-2: 33.333Mhz active Crystal Oscillator on the Core Board