Alinx AX7021 - Gigabit Ethernet Interface

ZYNQ FPGA Development Board AX7021 User Manual
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3.2 Gigabit Ethernet interface
The AX7021 has five Gigabit Ethernet interfaces on the carrier board, one
of which is the connected PS system side. The Ethernet interface is connected
to the logical IO port of the PL. The 4-port Gigabit Ethernet interface connected
to the PL side needs to be mounted to ZYNQ's AXI bus system by call IP
program.
The Ethernet chip uses Micrel's KSZ9031RNX Ethernet PHY chip to
provide network communication services to users. The Ethernet PHY chip on
the PS side is connected to the GPIO interface of the PSNK501 of the PS side
of ZYNQ. The Ethernet PHY chip on the PL side is connected to the IO of
BANK33 and BANK34. The KSZ9031RNX chip supports 10/100/1000 Mbps
network transmission rate and data communication with the MAC layer of the
Zynq7000 system through the RGMII interface. KSZ9031RNX supports
MDI/MDX adaptation, various speed adaptive, Master/Slave adaptation, MDIO
bus for PHY register management.
After power-on, the KSZ9031RNX detects the level status of some specific
IOs to determine their working mode. Table 3-2-1 describes the default settings
after the GPHY chip is powered on.
Configuration Pin
Instructions
Configuration value
PHYAD[2:0]
MDIO/MDC Mode PHY Address
PHY Address 011
CLK125_EN
Enable 125Mhz clock output
selection
Enable
LED_MODE
LED light mode configuration
Single LED light mode
MODE0~MODE3
Link adaptation and full duplex
configuration
10/100/1000 adaptive,
compatible with full-duplex,
half-duplex
Table 3-2-1: Default setting after power-on of the KS GPHY chip
When the network is connected to Gigabit Ethernet, the data transmission
of ZYNQ and PHY chip KSZ9031RNX is communicated through the RGMII bus,
the transmission clock is 125Mhz, and the data is sampled on the rising edge
and falling samples of the clock.
When the network is connected to 100M Ethernet, the data transmission of