Alinx AX7021 - Page 37

ZYNQ FPGA Development Board AX7021 User Manual
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ZYNQ and PHY chip KSZ9031RNX is communicated through the RMII bus,
and the transmission clock is 25Mhz. Data is sampled on the rising edge and
falling samples of the clock. Figure 3-2-1 and Figure 3-2-2 detailed the
connection of the ZYNQ chip end Ethernet PHY chip:
Figure 3-2-1: The connection of the ZYNQ PS end and PHY chip
Figure 3-2-2: The connection of the 4 ZYNQ PL end and PHY chip