Alinx AX7021 - USB2.0 Host Interface

ZYNQ FPGA Development Board AX7021 User Manual
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ETH4(PL) Pin Assignment:
Signal Name
Pin Name
Pin Number
Explain
PHY5_TXCK
B33_L24_N
AB15
RGMII Send clock
PHY5_TXD0
B33_L20_P
V13
Send data bit０
PHY5_TXD1
B33_L20_N
W13
Send data bit1
PHY5_TXD2
B33_L23_P
Y13
Send data bit2
PHY5_TXD3
B33_L23_N
AA13
Send data bit3
PHY5_TXCTL
B33_L24_P
AB14
Send enable signal
PHY5_RXCK
B33_L13_P
W17
RGMII Receive clock
PHY5_RXD0
B33_L18_N
AB16
Receive data Bit0
PHY5_RXD1
B33_L18_P
AA16
Receive data Bit1
PHY5_RXD2
B33_L21_N
Y15
Receive data Bit2
PHY5_RXD3
B33_L21_P
W15
Receive data Bit3
PHY5_RXCTL
B33_L13_N
W18
Receive data valid signal
PHY5_MDC
B33_L12_P
Y18
MDIO Management clock
PHY5_MDIO
B33_L12_N
AA18
MDIO Management data
3.3 USB2.0 Host interface
There are 4 USB2.0 HOST interfaces on the AX7021 carrier board. The
USB2.0 transceiver uses a 1.8V, high-speed USB3320C-EZK chip that
supports the ULPI standard interface, and then expands the 4-port USB HOST
interface through a USB HUB chip USB2514. ZYNQ's USB bus interface is
connected to the USB3320C-EZK transceiver to achieve high-speed USB2.0
Host mode data communication. The USB3320C's USB data and control
signals are connected to the IO port of the BANK501 on the PS side of the
ZYNQ chip. The USB interface differential signal (DP/DM) is connected to the
USB2514 chip to extend the four USB ports. Two 24MHz crystal oscillators
provide system clocks for the USB3320C and USB2514 chips, respectively.
The USB interface is a flat USB interface (USB Type A), which allows
users to connect different USB Slave peripherals (such as USB mouse and
USB keyboard) at the same time. The carrier board also provides +5V power to
each USB interface
The schematic diagram of the ZYNQ processor, USB3320C-EZK chip,
USB2514 chip connection is shown as Figure 3-3-1