Alinx AX7021 - Page 39

ZYNQ FPGA Development Board AX7021 User Manual
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ETH1(PL) Pin Assignment:
Signal Name
Pin Name
Pin Number
Explain
PHY2_TXCK
B34_L17_N
R21
RGMII Send clock
PHY2_TXD0
B34_L5_P
N17
Send data bit０
PHY2_TXD1
B34_L5_N
N18
Send data bit1
PHY2_TXD2
B34_L14_P
N19
Send data bit2
PHY2_TXD3
B34_L14_N
N20
Send data bit3
PHY2_TXCTL
B34_L17_P
R20
Send enable signal
PHY2_RXCK
B34_L11_P
K19
RGMII Receive clock
PHY2_RXD0
B34_L7_P
J18
Receive data Bit0
PHY2_RXD1
B34_L7_N
K18
Receive data Bit1
PHY2_RXD2
B34_L1_P
J15
Receive data Bit2
PHY2_RXD3
B34_L1_N
K15
Receive data Bit3
PHY2_RXCTL
B34_L11_N
K20
Receive data valid signal
PHY2_MDC
B34_L2_N
J17
MDIO Management clock
PHY2_MDIO
B34_L2_P
J16
MDIO Management data
ETH2(PL) Pin Assignment:
Signal Name
Pin Name
Pin Number
Explain
PHY3_TXCK
B34_L3_P
K16
RGMII Send clock
PHY3_TXD0
B34_L12_P
L18
Send data bit０
PHY3_TXD1
B34_L10_N
L22
Send data bit1
PHY3_TXD2
B34_L10_P
L21
Send data bit2
PHY3_TXD3
B34_L3_N
L16
Send data bit3
PHY3_TXCTL
B34_L15_N
M22
Send enable signal
PHY3_RXCK
B34_L13_P
M19
RGMII Receive clock
PHY3_RXD0
B34_L20_N
P18
Receive data Bit0
PHY3_RXD1
B34_L16_N
P22
Receive data Bit1
PHY3_RXD2
B34_L16_P
N22
Receive data Bit2
PHY3_RXD3
B34_L15_P
M21
Receive data Bit3
PHY3_RXCTL
B34_L20_P
P17
Receive data valid signal
PHY3_MDC
B34_L13_N
M20
MDIO Management clock
PHY3_MDIO
B34_L21_N
T17
MDIO Management data
ETH3(PL) Pin Assignment:
Signal Name
Pin Name
Pin Number
Explain
PHY4_TXCK
B33_L17_P
AA17
RGMII Send clock
PHY4_TXD0
B33_L6_P
V18
Send data bit０
PHY4_TXD1
B33_L16_P
U17
Send data bit1
PHY4_TXD2
B33_L16_N
V17
Send data bit2
PHY4_TXD3
B33_L17_N
AB17
Send data bit3
PHY4_TXCTL
B33_L7_P
AA22
Send enable signal
PHY4_RXCK
B33_L14_P
W16
RGMII Receive clock
PHY4_RXD0
B33_L15_N
U16
Receive data Bit0
PHY4_RXD1
B33_L19_P
V14
Receive data Bit1
PHY4_RXD2
B33_L19_N
V15
Receive data Bit2
PHY4_RXD3
B33_L7_N
AB22
Receive data Bit3
PHY4_RXCTL
B33_L15_P
U15
Receive data valid signal
PHY4_MDC
B33_L14_N
Y16
MDIO Management clock
PHY4_MDIO
B33_L22_P
Y14
MDIO Management data