Alinx AX7021 - JTAGE Interface

ZYNQ FPGA Development Board AX7021 User Manual
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Figure 2-9-1: Reset button connection diagram
Figure 2-9-2: Reset Button on the Core Board
Reset Pin Assignment:
Signal Name
Pin Name
Pin Number
Explain
PS_POR_B
PS_POR_B_500
B5
Reset Key
Table 2-9-1: Reset Pin Assignment
2.10 JTAGE Interface
The JTAG test socket J1 is reserved on the AC7021 core board for
separate JTAG download and debugging of the core board. Figure 2-10-1 is the
schematic part of the JTAG port, which involves TMS, TDI, TDO, TCK, GND. ,
+3.3V these six signals.
Figure 2-10-1: JTAG interface part of the core board schematic