Alinx AX7021 - Page 38

ZYNQ FPGA Development Board AX7021 User Manual
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Figure 3-2-3: PS side Ethernet GPHY port on Carrier board
Figure 2-3-4: 4 PS side Ethernet GPHY port on the carrier port
ETH0(PS) Pin Assignment:
Signal Name
Pin Name
Pin Number
Explain
PHY1_TXCK
PS_MIO16_501
D6
RGMII Transmit clock
PHY1_TXD0
PS_MIO17_501
E9
Transmit data bit０
PHY1_TXD1
PS_MIO18_501
A7
Transmit data bit1
PHY1_TXD2
PS_MIO19_501
E10
Transmit data bit2
PHY1_TXD3
PS_MIO20_501
A8
Transmit data bit3
PHY1_TXCTL
PS_MIO21_501
F11
Transmit enable signal
PHY1_RXCK
PS_MIO22_501
A14
RGMII Receive clock
PHY1_RXD0
PS_MIO23_501
E11
Receive data Bit0
PHY1_RXD1
PS_MIO24_501
B7
Receive data Bit1
PHY1_RXD2
PS_MIO25_501
F12
Receive data Bit2
PHY1_RXD3
PS_MIO26_501
A13
Receive data Bit3
PHY1_RXCTL
PS_MIO27_501
D7
Receive data valid signal
PHY1_MDC
PS_MIO52_501
D10
MDIO Management clock
PHY1_MDIO
PS_MIO53_501
C12
MDIO Management clock