Alinx AXU4EV-E - Page 15

ZYNQ Ultrascale + FPGA Board AXU4EV-E User Manual
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The hardware connection of DDR4 SDRAM on the Pl Side is shown in
Figure 2-3-2:
Figure 2-3-2: DDR3 DRAM schematic diagram
PS Side DDR4 DRAM pin assignment:
Signal Name
Pin Name
Pin Number
PS_DDR4_DQS0_P
PS_DDR_DQS_P0_504
AF21
PS_DDR4_DQS0_N
PS_DDR_DQS_N0_504
AG21
PS_DDR4_DQS1_P
PS_DDR_DQS_P1_504
AF23
PS_DDR4_DQS1_N
PS_DDR_DQS_N1_504
AG23
PS_DDR4_DQS2_P
PS_DDR_DQS_P2_504
AF25
PS_DDR4_DQS2_N
PS_DDR_DQS_N2_504
AF26
PS_DDR4_DQS3_P
PS_DDR_DQS_P3_504
AE27
PS_DDR4_DQS3_N
PS_DDR_DQS_N3_504
AF27
PS_DDR4_DQS4_P
PS_DDR_DQS_P4_504
N23
PS_DDR4_DQS4_N
PS_DDR_DQS_N4_504
M23
PS_DDR4_DQS5_P
PS_DDR_DQS_P5_504
L23
PS_DDR4_DQS5_N
PS_DDR_DQS_N5_504
K23
PS_DDR4_DQS6_P
PS_DDR_DQS_P6_504
N26