AMD VCU118 - Page 26

VCU118 Board User Guide 26
UG1224 (v1.5) March 15, 2023
Chapter3: Board Component Descriptions
The connections between the C2 80-bit interface DDR4 component memories (U135-U139)
and XCVU9P banks 40, 41, and 42 are listed in Table 3-3.
C15 DDR4_C1_A4 SSTL12_DCI N3 A4 U60-U64
A13 DDR4_C1_A5 SSTL12_DCI P8 A5 U60-U64
A14 DDR4_C1_A6 SSTL12_DCI P2 A6 U60-U64
A15 DDR4_C1_A7 SSTL12_DCI R8 A7 U60-U64
A16 DDR4_C1_A8 SSTL12_DCI R2 A8 U60-U64
B12 DDR4_C1_A9 SSTL12_DCI R7 A9 U60-U64
C12 DDR4_C1_A10 SSTL12_DCI M3 A10/AP U60-U64
B13 DDR4_C1_A11 SSTL12_DCI T2 A11 U60-U64
C13 DDR4_C1_A12 SSTL12_DCI M7 A12/BC_B U60-U64
D15 DDR4_C1_A13 SSTL12_DCI T8 A13 U60-U64
G15 DDR4_C1_BA0 SSTL12_DCI N2 BA0 U60-U64
G13 DDR4_C1_BA1 SSTL12_DCI N8 BA1 U60-U64
H13 DDR4_C1_BG0 SSTL12_DCI M2 BG0 U60-U64
H14 DDR4_C1_A14_WE_B SSTL12_DCI L2 WE_B/A14 U60-U64
H15 DDR4_C1_A15_CAS_B SSTL12_DCI M8 CAS_B_A15 U60-U64
F15 DDR4_C1_A16_RAS_B SSTL12_DCI L8 RAS_B/A16 U60-U64
F14 DDR4_C1_CK_T DIFF_SSTL12_DCI K7 CK_T U60-U64
E14 DDR4_C1_CK_C DIFF_SSTL12_DCI K8 CK_C U60-U64
A10 DDR4_C1_CKE SSTL12_DCI K2 CKE U60-U64
E13 DDR4_C1_ACT_B SSTL12_DCI L3 ACT_B U60-U64
G10 DDR4_C1_PAR SSTL12_DCI T3 PAR U60-U64
C8 DDR4_C1_ODT SSTL12_DCI K3 ODT U60-U64
F13 DDR4_C1_CS_B SSTL12_DCI L7 CS_B U60-U64
R17 DDR4_C1_ALERT_B SSTL12_DCI P9 ALERT_B U60-U64
N20 DDR4_C1_RESET_B LVCMOS12 P1 RESET_B U60-U64
A20 DDR4_C1_TEN SSTL12_DCI N9 TEN U60-U64
Table3‐2: DDR4 Memory 80‐bit I/F C1 to FPGA U1 Banks 71, 72, and 73 (Cont’d)
FPGA (U1)
Pin
Schematic Net Name I/O Standard
Component Memory
Pin # Pin Name Ref. Des.
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