VCU118 Board User Guide 98
UG1224 (v1.5) March 15, 2023
Chapter3: Board Component Descriptions
The VCU118 evaluation board supports the VITA 57.4 FPGA mezzanine card plus (FMC+ or
FMCP) specification by providing a subset implementations of the high pin count
connectors at J22 (HSPC). FMC+ connectors use a 14 x 40 form factor, populated with 560
pins. The connector is keyed so that a mezzanine card, when installed on the VCU118
evaluation board, faces away from the board.
J22 FMC+ Connector Type
• Samtec SEAF series, 1.27 mm (0.050 in) pitch. Mates with SEAM series connector. More
information about SEAF series connectors is available at the Samtec website [Ref 26].
More information about the VITA 57.4 FMC+ specification is available at the VITA FMC
Marketing Alliance website [Ref 27].
• The 560-pin FMC+ connector defined by the FMC specification (see Appendix A, VITA
57.1 and 57.4 FMC Connector Pinouts) provides connectivity for up to:
°
160 single-ended or 80 differential user-defined signals
°
24 transceiver differential pairs
°
6 transceiver differential clocks
°
4 differential clocks
°
239 ground and 19 power connections
Notes:
1. U30 MAX15301 VADJ_1V8_FPGA voltage regulator PGOOD level-shifted by U44.
2. FPGA U1 JTAG TCK, TMS pins AE13, AF15 are buffered by U19 SN74AVC8T245.
3. J2 HPC1 TDO-TDI connections to U132 HPC1 FMC JTAG bypass switch (N.C. normally closes/bypassing J2 until an FMC card
is plugged into J2).
4. FMC_HPC1_PRSNT_M2C_B is the HPC1 FMC JTAG bypass switch U132.4 OE control signal and is also connected to the FPGA
U1 pin BB7 via level shifter U44.
5. Connected to the FPGA U1 pins AL24/AM24 IIC_MAIN_SDA/SCL via IIC MUX U80.
6. HPC1 FMC signal FMC_HPC1_PG_M2C is connected to the FPGA U1 pin BA7 via level shifter U44.
Table3‐31 : J2 VITA 57.1 FMC HPC1 Connections (Cont’d)
J2
FMC
HPC1
Pin
Schematic Net Name
I/O
Standard
FPGA
(U1)
Pin
J2
FMC
HPC1
Pin
Schematic Net Name
I/O
Standard
FPGA
(U1) Pin
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