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6-12 ML4803A

EMULATION

COMMANDS

This sec tion pro vides an al pha bet i cal list ing of the GPIB com mands (mne mon -

ics) used to pro gram the Model ML2400A Se ries Power Me ter in ML4803A

mode. The em u la tion mode can be set through the front panel

or through the GPIB com mand EMUL (page 6-89 ).

All ML4803A GPIB com mands that use pa ram e ters must not

have a space be -

tween the com mand header and the pa ram e ter. Mul ti ple parameters must be

sep a rated by semi co lons.

Mul ti ple com mands may be sent on the same line, but must be sep a rated by

spaces.

The for mat for ML4803A GPIB com mands is:

<com mand header><pa ram e ter 1>;<pa ram e ter n>;...

The end of the com mand text must be ter mi nated with a line feed char ac ter

(0Ah, dec i mal 10) or a GPIB End of Trans mis sion State (EOI), or both.

The ML4803A has an ar ray of mem ory ad dresses that each hold a struc ture of

four val ues; Fre quency, Cal fac tor, Off set, and Ref er ence. The data held for an

en tered fre quency is not au to mat i cally ap plied, but only ap plied if that mem -

ory ad dress is called. The fre quency value is only a ref er ence to the op er a tor

for which the cal fac tor and other data is rel e vant. These mem ory ad dress sets

of data are only avail able via the GPIB in ML4803A em u la tion mode.

SRQ’s The startup and de fault mode of op er a tion for the ML4803A is to set an SRQ

off then on again for ev ery read ing when avail able. This has the af fect of puls -

ing the SRQ line very quickly and would make it very dif fi cult to use the

ML4803A with other de vices on the GPIB bus that wish to com mu ni cate via

SRQ’s. These SRQ’s can be turned off tem po rarily by the ‘SRQ0’ com mand.

The SRQs will start again as soon as any data is re quested from the ML4803A.

Sta tus Byte The fol low ing ta ble and di a gram de fine the Sta tus Byte.

Bit 0 Zero ex e cu tion Bit set dur ing ze ro ing. When ze ro ing is com plete the bit is

cleared and the ODR bit and RQS bits are re set.

Bit 1 Cal ex e cu tion Bit is set dur ing the Cal 0 dBm.

Bit 3 Out put data ready ODR bit is cleared and set for ev ery read ing when made.

This is done in sync with the RQS bit giv ing an SRQ.

Bit 5 Com mand er ror Set on re ceiv ing an un rec og nized com mand. The bit is

cleared by read ing the sta tus byte.

Bit 6 RQS bit In di cates that the de vice is re quir ing ser vice (SRQ).

ML2400A OM 6-87

GPIB OPERATION ML4803A EMULATION COMMANDS

Anritsu ML2400A Series User Manual

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