14 english
6 
SSI interface
6.1  Principle
SSI stands for Synchronous Serial Interface and describes 
a digital synchronous interface with a differential clock line 
and a differential data line.
With the first falling cycle edge, the data word to be output 
is buffered in the transducer to ensure data consistency. 
Data output takes place with the first rising cycle flank, i.e. 
the transducer supplies a bit to the data line for each rising 
cycle edge. In doing so, the line capacities and delays of 
drivers t
v
 when querying the data bits must be taken into 
account in the controller. 
The max. clock frequency f
Clk
 is dependent on the cable 
length (see Technical data on page20, Fig. 8-2). The t
m 
time, also called monoflop time, is started with the last 
falling edge and is output as the low level with the last 
rising edge. The data line remains at low until the t
m
 time 
has elapsed. Afterwards, the transducer is ready again to 
receive the next clock package.
k
ta
T
Clk
t
v
t
v
Clk
Data
MSBLSB
T
Clk
1234 5nn+1
t
m
Clk
Data
T
A
T
Clk
= 1/f
Clk
SSI clock period, SSI clock frequency
T
A
= 1/f
A
Sampling period, sampling rate
n Number of bits to be transmitted (requires n+1 clock impulses)
t
m
= 2·T
Clk
Time until the SSI interface is ready again
t
v
= 150ns Transmission delay times (measured with a 1m cable)
With the BTL7-S5_ _B-M…, position data is determined 
and output in a timely manner and synchronous to the 
external sampling period. For synchronous operation, the 
sampling period T
A
 must be in the range 
T
A,min
≤T
A
≤16ms. The transducer switches to 
asynchronous operation outside of this range. If the 
minimum sampling time is undercut, the transducer 
outputs the same position value several times. The 
external sampling rate is then greater than the internal rate. 
In addition, T
A
 must be long enough so that the next clock 
package does not occur in the t
m
 range of the previous 
package.
BTL7-S5 __ (B)-M ____ -A/B/Y/Z(8)-S32/S115/S140/S147/KA __ /FA __
Micropulse Transducer - Rod Style