Multi-DM™ User Manual Section 10 - Reference Information
BMC Document Number: DOC-0009 Rev. 5.2 Page 58
10.8 Multi Driver Dataflow and Error Detection
To control the high voltage power supplies, the Multi Driver contains five (5)
digital-to-analog converters (DACs), each with 32 channels, for a total of 160 channels.
Of these,
• 140 channels are output to the high voltage power supplies to drive the DM.
• 4 channels are reserved for use as low voltage outputs on the Driver
Auxiliary Output DE-9 connector.
• 16 channels are un-used.
Data flows from the PC to the DM as follows:
1. Data for all of the actuators consists of 160 16-bit (2 bytes) output levels,
which translates into 320 bytes of data. In the PC, this is bundled with a checksum
and sent across the USB interface to the Multi Driver.
2. In the Multi Driver, the built in USB protocol verifies the checksum, and,
if validated, loads the data into a FIFO buffer. If the checksum is not validated
the data send is retried.
3. The DACs are loaded in parallel, one channel at a time. First, data from the FIFO
is pulled out in groups of 5 16-bit words, one for each of the 5 DACs.
This data is formatted properly for the DACs, and then loaded into the same channel
in each DAC. This process takes 1µs.
4. The cycle repeats with 5 new words for the next DAC channel until all 32 channels
of the DAC are loaded. This takes in total 32µs.
Note that if the FIFO does not go empty exactly on a 320 byte boundary,
an error condition, handled as described below, is generated.
5. Once fully loaded, the data in the DACs is immediately used to control
the high voltage power supply outputs to the DM actuators.
6. After the last DAC channel is loaded, and a short 1µs pause, the hardware is ready
for the next packet if and when one is sent.
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