Table 6-2.
PET
Memory
Map
(Rev.
3 ROMs) (Continued)
Memory Address Sample Value
Decimal
59456
59457
59458
59459
59460-59461
59462-59463
59464
59465
59466
59467
59468
59469
59470
59471
Hexadecimal
E840
E841
E842
E843
E844-E845
E846-E847
E848
E849
E84A
E84B
E84C
E84D
E84E
E84F
Decimal
223
255
30
o
29241
65535
147
217
o
o
14
o
128
255
Hexadecimal
DF
FF
lE
00
7239
FFFF
93
D9
00
00
OE
00
80
FF
Description
Parallel User Port
VIA
(59456-59471
)
1/0 Port B
207=#2
cassette motor
on
223=#2
cassette motor
off
WAIT
59456.23.23
waits
for
vertical
retrace of display
Bit 1
~PB1
INFRD
on
IEEE
connector)
output
line
Bit
3~PB3IATN
on
IEEE
connector)
output
!ine
1/0 Port A
with
handshaking
Data Direction register for
1/0 Port B
Data Direction register for 1/0 Port A
For
each
bit
1
~outpul.
O~input
~O
ail input
~255
ail output
(Law. high arder)
Read
Timer
1.
Counter;
write
ta Timer 1 Latch and (high byte)
initiate count
(Law. high arder)
Read
Timer 1 Latch
Read
Tlmer 2 Counter
low
byte and reset
mterrupl.
write
ta Timer 2
low
byte
PEEK
(59464) Clock decrements every
microsecond
POKE
59454.n sets
SR
rate of shift from
hlgh
(n~O)
ta low
(n~255)
for musIc from
User Port
Read
Timer 2 Counter high byte;
write
ta
Timer 2 high byte and reset interrupt
PEEK
(59465) Clock decrements every
millisecond
Seriai 1/0 Shift register
(SR)
POKE
59466.
15
or 85 ta generate
Square wave output at
CB2
for playing
music from User PorI.
Auxiliary Control register
=
16
Sets
SR
ta free-running mode for
music from User Port
~O
for proper operation
of
tape drive
Peripheral Control register
~
12 for graphics
on
shifted
characters
=14
for lower-case letters
on
shifted
characters
Interrupt
Flag
register
Interrupt enable register
1/0 Port A
without
handshaking
61440-61621
344
FOOO-FOB5
Page
241-256 Operating System 161440-65535)
Monitor messages
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