Contec SBC Series - Page 73

7. BIOS Setup
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PC-686BX(NLX)-LV, PC-686BX(NLX)-LVV
SDRAM CAS Latency Time
The CAS latency time can be set to either 2/2 or 3/3 of HCLK. The system designer
needs to set the value in this field based on the installed DRAM and CPU DRAM
installation specifications.
Selection options: 2, 3
DRAM Data Integrity Mode
Select the parity and ECC (error correction code) setting based on the type of DRAM
installed.
Selection options: Non-ECC, ECC
System BIOS Cacheable
If enabled, caching of F0000h-FFFFFh of the BIOS ROM is permitted. This results
in faster system performance.
However, a system error may occur if a program writes to this memory area.
Selection options: Enabled, Disabled
Video BIOS Cacheable
If enabled, caching of the video BIOS is permitted. This results in faster system
performance. However, a system error may occur if a program writes to this memory
area.
Selection options: Enabled, Disabled
Video RAM Cacheable
If enabled, caching of video RAM is permitted. This results in faster system
performance. However, a system error may occur if a program writes to this memory
area.