Execution
timE
For
176:
Instruction
issue except for 034-037, 100-137, 176,
177:
1
CP
Instruction
issue for
above
exceptions:
(VL)
+ 4
CPs
Vi
ready
14
CPs
if
(VL)
~
5
Vi
ready
(VL)
+ 9
CPs
if
(VL)
> 5
For
177:
Instructi
on
issue except for 034-037, 100-137, 176,
177:
1
CP
Instruction
issue
for
above
exceptions:
(VL)
+ 5
CPs
Vj
ready 5
CPs
if
(VL)
~
5
V j ready
(VL)
CPs
if
(VL·)
>
c=
Special cases
T~e
increment,
(A
o
),
= 1
if
k = 0
Chain
slot
issue
is
9
CPs
if
full
speed for 176, blocked for
177
Block
I/O
references
Block
034
- 037,
100
- 137, 176,
177
(Ak)
determines speed
control.
There are
16
memory
banks;
successive addresses are located in successive banks. References
to the
samp
bank
can
be
made
every 4
CPs
or
more.
Incrementing
(Ak)
by
16
t
places successive
memory
references in the
same
bank,
so
a
word
is
transferred
every 4
CPs.
If
(Ak)
is
incremented
by
8,tt
every other reference
is
to the
same
bank
and
words
can
transfer
every 2
CPs.
With
any
address incrementing
that
allows
4
CPs
before addressing the
same
bank, the
words
can
transfer
each
CPo
Memory
reference out of
limits
will allow 6
CPs
+ 2 parcels to issue.
For
176, a
parity
error
will allow a
minimum
of
16
CPs
+ 2 parcels
to issue
and
a
maximum
of
(VL)
+
15
CPs
+ 2 parcels to issue.
t 8 places for 8-bank
memory
option. Refer to section
5.
tt
4 places for 8-bank
memory
option. Refer to section
5.
2240004
4-74
E
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