VECTOR
CONTROL
REGISTERS
Two
registers
are associated with vector
registers
and
provide control
information
needed
in the performance of vector operations.
They
are
the vector length
(VL)
register
and
the vector
mask
(VM)
register.
·VL
register
The
7-bit
vector length
register
can
be
set
to 0 through
100
s
and
specifies
the length of
all
vector operations performed
by
vector
instructions
and
the length of the vectors held
by
the V
registers.
It
controls the
number
of operations performed for
instructions
140
through
177.
The
VL
register
may
be
set
to
an
A
register
value through
use
of the
0020
instruction.
Cray
Research cautions users
against
changing
VL
between
operations
that
may
chain together.
In
code
sequences
where
the vector length
is
increased,
unexpected
results
may
occur.
Suppose, for example,
that
during a vector sequence the contents of
VL
are
changed
to a
larger
value
and
a second operation
is
initiated
to chain to
the
first
operation.
The
user
may
expect
that
the second operation will
use
the
results
of the
first
operation
and
the operands in the
register
unaltered
by
the
first
operation.
However,
when
the
instructions
chain
together,
the second
instruction
does
not receive the
anticipated
operands
beyond
the
VL
specified
for
the
first
operation.
The
user
who
intends to
use the system in
this
manner
must
take care to avoid chained operations.
Although there
may
be
applications
of the
characteristic
produced
by
chained operations with
different
contents
for
VL,
Cray
Research takes
no
responsibility
for
its
use. Chained operation cannot
be
assured since
I/O
interrupts
may
"break" the chain.
VM
register
The
vector
mask
register
has
64
bits,
each of
which
corresponds to a
word
element in a vector
register.
Bit 0 corresponds to element 0,
bit
63
to
element
63.
The
mask
is
used
in conjunction with vector
merge
and
test
instructions
to allow operations to
be
performed
on
individual vector
elements.
The
vector
mask
register
may
be
set
from
an
S
register
through the
003
instruction
or
may
be
created
by
testing
a vector
register
for
condition
using the
175
instruction.
The
mask
controls element
selection
in the
vector
merge
instructions
(146
and
147).
2240004
3-6
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