S
REGISTERS
The
eight
64-bit
S
registers
are the principal
scalar
registers
for the
CPU.
These
registers
serve
as
the source
and
destination for operands
in the execution of
scalar
arithmetic
and
logical
instructions.
The
related functional units perform both integer
and
floating point
arith-
metic operations.
S
registers
may
furnish
one
operand in vector
instructions.
Single-word
transmissions of data
between
an
S
register
and
an
element of a V
register
are also possible.
Data
can
move
directly
between
memory
ana
S
reqisters
or
can
be
placed in
T
registers
as
an
intermediate step.
This
allows buffering of
scalar
operands
between
S
registers
and
memory.
Data
can
also
be
transferred
between
A
and
S
registers.
Another
use
of the S
registers
is
for
setting
or reading the vector
mask
(VM)
register
or the real-time clock
register.
At
most,
one
S
register
can
be
entered with data during
each
clock period.
Issue of
an
instruction
is
delayed
if
it
would
cause data to arrive
at
the
S
registers
at
the
same
time
as
data already being processed
which
is
scheduled to arrive
from
another source.
When
an
instruction issues
that
will deliver
new
data to
an
S
register,
a
reservation
is
set
for
that
register
to prevent issue of instructions
that
read the
register
until the
new
data
has
been
delivered.
In
this
manual,
the S
registers
are individually referred to
by
the
letter
S
and
a
numeric
subscript in the range 0 through
7.
Instructions reference
S
registers
by
allowing specification of the subscript
as
the
i,
j,
or k
designator
as
described in section 4 of
this
manual.
The
only
register
to
which
an
implicit
reference
is
made
is
the
So
register.
The
use
of
this
register
is
implied in the following
branch
instructions:
014
through
017.
Refer to section 4 for additional information concerning the
use
of S
registers
by
instructions.
2240004
3-7
E
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