At
most,
one
A
register
can
be
entered with data during
each
clock period.
Issue of
an
instruction
is
delayed
if
it
would
cause data to arrive
at
the
A registers
at
the
same
time
as
data already being processed
which
is
scheduled to arrive
from
another source.
When
an
instruction issues that will deliver
new
data to
an
A
register,
a
reservation
is
set
for
that
register
to prevent issue of instructions that
read the
register
until the
new
data
has
been
delivered.
In
this
manual,
the A registers are individually referred to
by
the
letter
A
and
a
numeric
subscript in the
range
0 through
7.
Instructions reference
A registers
by
allowing specification of the subscript
as
the h,
i,
j,
or k
designator
as
described in section 4 of
this
manual.
The
only
register
to
which
an
implicit reference
is
made
is
the
Ao
register.
The
use
of
this
register
is
implied in the following instructions:
010
through
013
034
through
037
176
and
177
Refer
to section 4 for additional information concerning the
use
of A
registers
by
instructions.
B
REGISTERS
There
are sixty-four 24-bit B registers in the computation section.
The
B
registers are
used
as
intermediate storage for the A
registers.
Typically,
the B registers will contain data to
be
referenced repeatedly over a
sufficiently
long
span
that
it
would
not
be
desirable to retain the data
in
either
A registers or in
memory.
Examples
of uses are
loop
counts,
variable array
base
addresses,
and
dimensions.
The
transfer of a value
between
an
A
register
and
a B
register
requires
only
one
clock period. A block of B registers
may
be
transferred to or
from
memory
at
the
maximum
rate of
one
24-bit value per clock period.
No
reservations are
made
for B registers
and
no
instructions
can
issue
during block transfers to
and
from
B
registers.
2240004
3-9
E
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